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CMOS PLL Synthesizers:Analysis and Design(CMOS锁相环:分析和设计)

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CMOS PLL Synthesizers:Analysis and Design
中文名:
CMOS锁相环:分析和设计

Author: Keliu Shu,Edgar Sánchez-Sinencio
Publisher: Springer; 1 edition (November 12, 2004)
Language: English
ISBN-10: 0387236686
ISBN-13: 978-0387236681
Pages: 215
Format: PDF,12.5MB
Contents:
1 Introduction
 1.1 MOTIVATION
 1.2 SUMMARY OF BOOK
 1.3 BOOK ORGANIZATION
 REFERENCES
2 Frequency Synthesizer for Wireless Applications
 2.1 DEFINITION AND CHARACTERISTICS
 2.2 PHASE NOISE AND TIMING JITTER
  2.2.1 Phase noise and spurious tone
  2.2.2 Timing jitter
 2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER
  2.3.1 Direct analog frequency synthesizer
  2.3.2 Direct digital frequency synthesizer
  2.3.3 PLL-based frequency synthesizer
  2.3.4 DLL-based frequency synthesizer ~...
  2.3.5 Hybrid frequency synthesizer :.
  2.3.6 Summary and comparison of synthesizers
 2.4 FREQUENCY SYNTHESIZER FOR WIRELESS TRANSCEIVERS
 2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER
 REFERENCES
3 PLL Frequency Synthesizer
 3.1 PLL FREQUENCY SYNTHESIZER BASICS
  3.1.1 Basic building blocks of charge-pump PLL
  3.1.2 Continuous-time linear phase analysis
  3.1.3 Locking time
  3.1.4 Tracking and acquisition
 3.2 FAST-LOCKING TECHNIQUES
  3.2.1 Bandwidth gear-shifting
  3.2.2 VCO pre-tuning
 3.3 DISCRETE-TIME ANALYSIS AND NONLINEAR MODELING
  3.3.1 z-domain transfer function and stability analysis
  3.3.2 Nonlinear dynamic behavior modeling
 3.4 DESIGN EXAMPLE: 2.4GHZ INTEGER-N PLL FOR BLUETOOTH
 REFERENCES
4 ∑△ FractionaI-N PLL Synthesizer
 4.1 ∑△ FRACTIONAL-N FREQUENCY SYNTHESIZER
  4.1.1 ∑△ quantization noise to phase noise mapping
  4.1.2 ∑△ quantization noise to timing jitter mapping
 4.2 A COMPARATIVE STUDY OF DIGITAL ∑△ MODULATORS
  4.2.1 Design considerations
  4.2.2 Four types of digital ∑△ modulators
  4.2.3 Summary of comparative study
 4.3 OTHER APPLICATIONS OF EA-PLL
  4.3.1 Direct digital modulation
  4.3.2 Frequency-to-digital conversion
 4.4 MODELING AND SIMULATION OF ∑△-PLL
 4.5 DESIGN EXAMPLE: 900MHz ∑△-PLL FOR GSM
 REFERENCES
5 Enhanced Phase Switching Prescaler
 5.1 PRESCALERARCHITECTURE
  5.1.1 Conventional prescaler
  5.1.2 Phase switching prescaler
  5.1.3 Injection-locked prescaler
  5.1.4 Summary and comparison of prescalers
 5.2 ENHANCED PHASE-SWITCHING PRESCALER
 5.3 CIRCUIT DESIGN AND SIMULATION RESULTS
  5.3.1 Eight 45~-spaced phases generation
  5.3.2 8-to-1 multiplexer
  5.3.3 Switching control circuit
  5.3.4 Asynchronous frequency divider
 5.4 DELAY BUDGET IN THE SWITCHING CONTROL LOOP
 5.5 SPURS DUE TO NONIDEAL 45 PHASE SPACING
 REFERENCES
6 Loop Filter With Capacitance Multiplier
 6.1 LOOP FILTER ARCHITECTURE
  6.1.1 Passive loop filter
  6.1.2 Dual-path loop filter
  6.1.3 Sample-reset loop filter
  6.1.4 Other loop filter architectures
  6.1.5 Summary and comparison of loop filters
 6.2 LOOP FILTER AND CHARGE-PUMP NOISE MAPPING
 6.3 LOOP FILTER WITH CAPACITANCE MULTIPLIER
  6.3.1 Third-order passive loop filter
  6.3.2 Capacitance multiplier
  6.3.3 Simulation of loop filter with capacitance multiplier
  6.3.4 Noise consideration
 REFERENCES
7 Other Building Blocks of PLL
 7.1 VCO
  7.1.1 LC-VCO
  7.1.2 Varactor
  7.1.3 Inductor
  7.1.4 VCOphase noise
  7.1.5 Layout
 7.2 PHASE-FREQUENCY DETECTOR
  7.3 CHARGE-PUMP
  7.3.1 Reference spur
  7.3.2 Charge pump architectures
 7.4 PROGRAMMABLE DIVIDER
 7.5 DIGITAL MODULATOR
 7.6 CHIP LAYOUT
 REFERENCES
8 Prototype Measurement Results
 8.1 PRESCALER MEASUREMENT
 8.2 LOOP FILTER MEASUREMENT
 8.3 PLL MEASUREMENT
 REFERENCES
9 Conclusions
内容简介
  本书是一本关于小型sigma-delta频率综合器方面的优秀著作。作者分别从系统级和电路级对频率综合器的设计进行了阐述。主要创新点在低功耗高速分频器和减少芯片面积的环路滤波器的电容设计上。该书涉及PLL的基础问题,内容全面翔实,由浅入深,对PLL的关键问题提出了解决方案。

Description:
  This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly.
  This book is conceived as a PLL synthesizer manual for both academia researchers and industry design engineers.


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[ 本帖最后由 Strawhat 于 2008-9-27 12:58 PM 编辑 ]
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licankao  士官⑥  发表于 2013-12-25 10:18:15  | 显示全部楼层
PLL的关键问题提出了解决方案。
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augusta  上尉  发表于 2013-10-23 11:26:00  | 显示全部楼层
好资料,谢谢分享,顶一下!
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电气化铁路  大将  发表于 2018-12-3 09:02:17  | 显示全部楼层
非常好的一本书.
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qche111  版主  发表于 2008-8-12 09:38:50  | 显示全部楼层
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CMOS PLL Synthesizers Analysis and Design.part2.rar

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qche111  版主  发表于 2008-8-12 09:41:07  | 显示全部楼层
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CMOS PLL Synthesizers Analysis and Design.part1.rar

4.88 MB, 阅读权限: 5, 下载次数: 260, 下载积分: 微元 3

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zhengjianchun  少校  发表于 2008-8-12 13:35:50  | 显示全部楼层
:30bb :30bb :30bb
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dannymu  士官⑥  发表于 2008-8-12 22:27:45  | 显示全部楼层
好书。。。。。。。。。。。。。。。。。。。。
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emiano    发表于 2008-8-13 18:21:26  | 显示全部楼层
提示: 作者被禁止或删除 内容自动屏蔽
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wystan  士官①  发表于 2008-8-15 14:40:38  | 显示全部楼层
kidjfklwjf lkddfewer
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l00117404  士官④  发表于 2008-8-23 02:47:30  | 显示全部楼层

THANK YOU VERY MUCH !!!

楼主真是好人啊!!!!!!!!!!!!!!!!!!!11
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hxb03041825  士官②  发表于 2008-8-29 10:13:39  | 显示全部楼层

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thank you!分享....................................
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chengbin55  中尉  发表于 2008-8-30 16:58:16  | 显示全部楼层
好资料,谢谢分享,顶一下!
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