Extreme Low-Power Mixed Signal IC Design:ص
1 Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Applications of Widely Adjustable Circuits and Systems . . . . . . . . . . . . 2
1.1.1 Performance Scalability and Requirements . . . . . . . . . . . . . . . . . 5
1.2 Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Analog Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Organization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Subthreshold MOS for Ultra-Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 MOS Technology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Device Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 I–V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Second Order Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Design Considerations in Subthreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1 PVT Variation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.2 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 Ultra-Low-Power Design Using SubthresholdMOS . . . . . . . . . . . . . . . . . 29
2.4.1 MOS Transistor Leakage Mechanisms . . . . . . . . . . . . . . . . . . . . . . 30
2.4.2 Leakage Reduction Techniques .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5 Impacts of Variation on Subthreshold CMOS Operation .. . . . . . . . . . . . 37
2.5.1 Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5.2 Energy Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.5.3 Optimal Design with Technology Scaling . . . . . . . . . . . . . . . . . . . 49
2.5.4 Supply Voltage and Threshold Voltage
Scaling for Optimal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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viii Contents
Part I Scalable and Ultra-Low-Power Digital Integrated Circuits
3 Subthreshold Source-Coupled Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2 Conventional SCL Topology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.2 Tradeoffs in Design of Strong-Inversion SCL Gates. . . . . . . . 67
3.3 Ultra-Low-Power Source-Coupled Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.1 High-Valued Load Device Concept . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.2 STSCL Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4 Design Issues and Performance Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.1 Power-Speed Tradeoffs in STSCL . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.2 Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.4.3 Replica Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.4.4 Minimum Operating Current .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.4.5 Global Process and Temperature Variation .. . . . . . . . . . . . . . . . . 86
3.4.6 Effect of Mismatch on Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.4.7 Minimum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.5.1 Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.5.2 Ring Oscillator and Frequency Divider. . . . . . . . . . . . . . . . . . . . . . 90
3.5.3 Multiplier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.6 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4 STSCL Standard Cell Library Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2 Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
4.2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
4.2.2 Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
4.2.3 Cell Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
4.2.4 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
4.2.5 LEF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
4.2.6 Template Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
4.3 Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
4.3.1 Series–Parallel Tail Bias Transistors . . . . . . . . . . . . . . . . . . . . . . . . .106
4.3.2 Constant Area Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
4.4 Demonstration Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
4.4.1 FIR Filter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
4.4.2 Sample FIR Filter Demonstrator Circuit . . . . . . . . . . . . . . . . . . . .109
4.5 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
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5 Subthreshold Source-Coupled Logic Performance Analysis . . . . . . . . . . . .115
5.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
5.2 Comparison with the CMOS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.2.1 Ultra-Low-Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.2.2 Power-Speed Tradeoff in STSCL . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5.2.3 Performance Analysis of CMOS Logic Circuits . . . . . . . . . . . .118
5.2.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.3 Performance Improvement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.3.1 Compound Logic Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
5.3.2 Using Source-Follower Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.3.3 Pipelining Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.4 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
5.4.1 STSCL with Source-Follower Buffer . . . . . . . . . . . . . . . . . . . . . . . .133
5.4.2 Pipelined Adder Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
5.4.3 Pipelined Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.5 Conclusions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
6 Low-Activity-Rate and Memory Circuits in STSCL . . . . . . . . . . . . . . . . . . . . .141
6.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
6.2 Power Efficiency in Low Activity Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.2.1 STSCL Topology Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
6.2.2 CMOS Topology Performance .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
6.2.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
6.3 Low-Leakage CMOS SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
6.4 Low Stand-By Current STSCL Memory Cell . . . . . . . . . . . . . . . . . . . . . . . .149
6.4.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
6.4.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
6.4.3 Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
6.4.4 Leakage Current Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6.6 Observations and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Part II Scalable and Ultra-Low-Power Analog Integrated Circuits
7 Widely Adjustable Continuous-Time Filter Design. . . . . . . . . . . . . . . . . . . . . . .161
7.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
7.2 Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
7.2.1 Low Power Folded-Cascode Amplifier . . . . . . . . . . . . . . . . . . . . . .162
7.2.2 Widely Adjustable Two-Stage Amplifier . . . . . . . . . . . . . . . . . . . .164
7.3 Transconductor-C Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
7.3.1 Proposed Biquadratic Filter Topology .. . . . . . . . . . . . . . . . . . . . . .166
7.3.2 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
7.3.3 Sixth Order gm-C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
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7.4 MOSFET-C Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
7.4.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
7.4.2 High-Valued Pseudo-Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
7.4.3 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
7.4.4 Second Order MOSFET-C Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
7.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
7.5.1 MOSFET-C Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
7.5.2 gm-C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
7.5.3 Figure of Merit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
7.6 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
8 Scalable Folding and Interpolating ADC Design. . . . . . . . . . . . . . . . . . . . . . . . . .187
8.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
8.2 Previous Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
8.3 Folding and Interpolating Analog-to-Digital Converter .. . . . . . . . . . . . .189
8.3.1 Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
8.3.2 Building Blocks and Design Tradeoffs . . . . . . . . . . . . . . . . . . . . . .192
8.4 Design of FAI ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
8.4.1 Circuit Topology .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
8.4.2 Ultra Low Power Resistor Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . .202
8.4.3 Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
8.4.4 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
8.5 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
8.5.1 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
8.5.2 FAI ADC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
8.6 Conclusion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
9 Widely Adjustable Ring Oscillator Based † ADC . . . . . . . . . . . . . . . . . . . . .215
9.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
9.2 Background .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
9.2.1 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
9.2.2 Improving the Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
9.3 Performance Scalability in Ring Oscillator Based † ADCs . . . . . . .218
9.3.1 Frequency Domain Adjustability . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
9.3.2 Dynamic Range Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
9.4 Top Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
9.4.1 Sources of Non-Ideality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
9.4.2 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
9.5 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
9.5.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
9.5.2 Logic Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
9.5.3 Current-Mode Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
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9.6 High Order Modulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
9.6.1 Analysis and Modeling .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
9.6.2 Behavioral Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
9.7 Simulations and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
9.8 Conclusion and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
10 Wide Tuning Range PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
10.1 Introduction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
10.2 Wide Tuning Range PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
10.2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
10.2.2 Wide Tuning Range CPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
10.2.3 Design Issues with Wide Tune PLLs . . . . . . . . . . . . . . . . . . . . . . . .249
10.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
10.3.1 Proposed PLL Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
10.3.2 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
10.3.3 Frequency Divider and Phase-Frequency
Detector (PFD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
10.3.4 Transconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
10.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
10.5 Conclusions.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
11 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
11.1 Main Contributions.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
11.2 Perspectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
List of Figures
1.1 Generic mixed-mode integrated system with a dynamic
power management for digital part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 A mixed-mode integrated system with dynamic power
management for the entire system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Conceptual timing diagram for two systems, one without
battery management system and the other one with a
system controlling the power dissipation with respect to
the battery voltage and data throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Conceptual diagram to explain the acceptable frequency
tuning range. Here, B0 represents the nominal biasing
condition and Bopt is the optimum bias point to maximize
the performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Power-efficient frequency-scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6 (a) Simulated tuning range of a CMOS (88) Cary–Save
multiplier achieved by adjusting the power supply
designed in CMOS 0.18m. The tuning range can be
extended even more by increasing the supply voltage
(VDD) above 0.5V. (b) Simulated power-delay product this
circuit versus supply voltage in different corner cases . . . . . . . . . . . . . . . . . . . 7
1.7 Programmable continuous-time integrator uses switchable
capacitors and transconductors to adjust the cutoff frequency . . . . . . . . . . . 8
1.8 A simplified switched-capacitor integrator. The capacitor
CS and the switches S1 and S2 are resembling a resistance.
The charge transfer of this resistance depends on the
clock frequency as well as the size of CS (sampling
capacitance). Therefore, the cutoff frequency of the
entire circuit depends on clock frequency and the size of
sampling capacitor as indicated in (1.3) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.9 Companding technique for implementing high DR circuits [29] . . . . . . . . 10
2.1 Exponential increase of number of transistors on a
single chip thanks to the CMOS technology scaling and
comparison to the prediction made in [8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
xiii
xiv List of Figures
2.2 (a) Structure of NMOS and PMOS devices. Symbol for
(b) NMOS and (c) PMOS devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Bias current dependence on temperature variations. In this
figure, the bias current is normalized to the nominal bias
current at T D 27ıC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Expected offset voltage at the input of a differential pair
circuit by technology scaling when minimum size devices
are utilized. Data values are extracted from [13] . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 Dependence of bias current, transconductance, and gm=I
on gate overdrive voltage: VGS VT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 ITRS predictions for device scaling and power dissipation
at 2001 [29] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.7 Leakage current sources in a MOS device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.8 I–V characteristics of an NMOS transistor and effect of
subthreshold slope factor on off current of the device . . . . . . . . . . . . . . . . . . . . 33
2.9 Stacking technique to reduce the leakage current.. . . . . . . . . . . . . . . . . . . . . . . . 37
2.10 Variation on: (a) ION current, (b) IOFF current, and
(c) delay of a NAND gate implemented in 65 nm CMOS
technology. (d) Typical value of D ION=IOFF . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.11 A sample CMOS inverter and the corresponding Butterfly
curve used for estimating NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.12 Comparing the estimated static noise margin based
on (2.69) and transistor level simulation results. (a)
The calculated VTC based on (2.69) including process
variations. (b) Static noise margin in comparison to the
transistor level simulations (c) Input–output crossover
point, XC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.13 (a) Parameter D versus . (b) NM0 based on analysis in
comparison to the NM0 value calculated using (2.75). This
graph also shows the lower limit on NM when process
variation is included. Here, VDD D 0:4V and VT D 0:5V. . . . . . . . . . . . . . . 43
2.14 (a) Noise margin of a subthreshold inverter biased
with VDD D VT0 in course of technology scaling. The
degradation of noise margin due to process variation has
been also shown. (b) Minimum NMOS transistor length
to have a positive noise margin in presence of process
variation. The results have been shown with and without
including the DIBL effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.15 (a) A chain of N identical CMOS gates. Note that the type
of logic gate used in the chain is arbitrary. (b) Modeling
the current waveform.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.16 Comparing noise margin resulted from transistor level
simulations with the results from (2.91) in 65 nm technology . . . . . . . . . . . 48
List of Figures xv
2.17 (a) Optimum energy consumption by technology scaling
(˛ D 0:1=N , N D 20, CL0 D 5 fF). (b) Corresponding
operating frequency for optimum energy consumption.
(c) Supply voltage in which energy consumption can
be minimized. This figure also shows the minimum
acceptable supply voltage to keep the noise margin
positive. (d) Ratio of the optimum supply voltage to device
threshold voltage by technology scaling. (e) Scaled device
length to have a positive NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.18 (a) Optimum energy consumption by technology scaling
(˛ D 0:9=N , N D 20, CL0 D 5 fF). (b) Corresponding
operating frequency for optimum energy consumption.
(c) Supply voltage in which energy consumption can
be minimized. This figure also shows the minimum
acceptable supply voltage to keep the noise margin
positive. (d) Ratio of the optimum supply voltage to device
threshold voltage by technology scaling. (e) Scaled device
length to have a positive NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.19 Minimum energy consumption in different technology
nodes when both supply voltage and threshold voltage
are optimized. The optimum values for supply voltage
and threshold voltage are also shown. Here, ˛ D 0:9=N .
The bottom figure shows the nominal, the best, and the
worst case operating frequency of the circuits in minimum
energy consumption point.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.20 Minimum energy-delay product in different technology
nodes when both supply voltage and threshold voltage
are optimized. The optimum values for supply voltage
and threshold voltage are also shown. Here, ˛ D 0:9=N .
The bottom figure shows the nominal, best, and worst
case operating frequency of the circuits in minimum EDP point . . . . . . . . 55
3.1 Design space for (a) static CMOS and (b) STSCL logic styles . . . . . . . . . . 62
3.2 A conventional SCL-based inverter/buffer circuit. The
switching part can be composed of a complex network of
NMOS source-coupled pairs to implement more complex
logic functions [7, 13]. The load resistances, RL, can be
implemented using PMOS devices biased in triode region.. . . . . . . . . . . . . . 63
3.3 Replica bias circuit used to control the resistivity of the
load devices .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4 SCL-based buffer chain to drive the load capacitance CL
at the desired data rate. The load resistance of the stage (i )
is RL;i and Ci is the total capacitance seen by RL;i . . . . . . . . . . . . . . . . . . . . . 68
xvi List of Figures
3.5 Current consumption in an SCL buffer chain for different
number of stages n and different voltage swing values
at the intermediate nodes (Vsw;i ) based on (3.27). In this
simulation, CL D2 pF, Vsw;in D 0:4V and it is assumed
that CIN should be smaller than 50fF. Inside the gray area,
it is not possible to achieve the desired CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.6 (a) Conventional PMOS load device, (b) proposed load
device, (c) I–V characteristics of the conventional PMOS
load (dotted) in comparison to the proposed device (solid
line), (d) measured I–V characteristics of the proposed
load device in comparison to the BSIM model (all data
obtained using 0.18m CMOS technology) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.7 Cross-section view of the proposed PMOS load device,
showing the parasitic components that contribute to its
operation in subthreshold regime .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.8 A very high-valued floating resistor composed of two
back to back PMOS devices: (a) circuit schematic and
(b) measured I–V characteristics of the controlled floating
resistor in CMOS 0.18m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.9 A subthreshold SCL gate and its replica bias circuit used
to control the output voltage swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.10 DC transfer characteristics of a STSCL gate designed
in 0.18-m CMOS and biased with ISS D100pA,
VSW D200mV: (a) voltage transfer characteristic and
(b) DC differential voltage gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.11 Mask layout of a 3-input XOR gate showing the area
occupied by the major components in CMOS 0.18m.
Note that the PMOS load device with their isolated n-wells
occupy a relatively small area compared to the NMOS
logic network and biasing transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.12 Measured gate delay for different tail bias currents in
0.18-m CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.13 DC transfer characteristics of an STSCL circuit designed
in 0.18-m CMOS technology. (a) Differential DC gain
versus desired VSW and tail bias current. (b) Noisemargin
and output voltage swing versus VSW and tail bias current .. . . . . . . . . . . . . . 80
3.14 Mismatch effect on STSCL gate performance. Variation
on gain, NM, voltage swing, and input referred offset are
shown. The value of NM depends highly on the output
voltage swing. Here, VSW D200mV and ISS D100pA for
200 runs ofMonte Carlo simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.15 Correlation between (a) variation on NM and offset
voltage and (b) variation on NM and output voltage swing,
based onMonte Carlo simulations in CMOS 65 nm. . . . . . . . . . . . . . . . . . . . . . 82
List of Figures xvii
3.16 Current of the load device when VSG D0V versus
temperature for CMOS 130, 90, and 65 nm technologies.
This current is mainly due to the forward-biased
source-bulk PN junction of the PMOS load device .. . . . . . . . . . . . . . . . . . . . . . 85
3.17 (a) Variation on gate delay due to the temperature
variations in 0.18m. (b) Delay variation over different
corner cases for CMOS 65 nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.18 Delay variation due to the device mismatch based on
(3.73). Here, it is assumed that AVT D5[mVm] and gate
area of PMOS load and tail bias NMOS devices are both
equal to S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.19 (a) Simulated DC transfer characteristics and DC gain
of an STSCL gate biased at ISS D1 nA. (b) Measured
transfer characteristics of an STSCL adder stage for two
different supply voltages (VDD D0:6V and 1.0V) and
different bias currents (ISS D1; 10, and 100nA). The test
circuit has been implemented in 0.18-mCMOS . . . . . . . . . . . . . . . . . . . . . . . . 90
3.20 Microphotograph of the test circuits: (a) ring oscillator
and (b) frequency divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.21 Measured oscillation frequency versus power dissipation
of the 8-stage ring oscillator based on the proposed STSCL
topology for VDD D 0:3, 0.4, and 1.0V. Corresponding
power-speed curves for a CMOS ring oscillator is shown as well . . . . . . . 92
3.22 (a) STSCL latch circuit schematic and (b) the topology of
the divide-by-8 circuit used for measurement.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.23 (a) Measured maximum frequency of operation versus
power dissipation of the divide-by-8 frequency divider
shown in Fig. 3.22 for VDD D0.4V and 1.0V. (b)
Simulated maximum operating frequency of STSCL
divider in different technologies (CMOS 90, 130, and 180 nm) . . . . . . . . . 93
3.24 Photomicrograph of the measured STSCL-based (88) bit
Carry–Save multiplier .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.25 (a) Measured total propagation delay of the proposed
STSCL multiplier versus tail bias current (ISS) for
different supply voltages in comparison to the simulation
results. (b) Comparing the power-delay product versus
delay for two (88) bit Carry–Save multiplier circuits
built with conventional CMOS and STSCL components .. . . . . . . . . . . . . . . . 95
4.1 Sample layout of an STSCL gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
4.2 The template for placing the cell and fat pins [1, 2] . . . . . . . . . . . . . . . . . . . . . .103
4.3 Footprints of the 1-level and the 2-level networks [1] . . . . . . . . . . . . . . . . . . . .105
4.4 Improving the cell driving strength by multiplying the tail
bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
4.5 Scaling the tail bias current using parallel and series configurations . . . .107
xviii List of Figures
4.6 Scaling driving strength by changing the bias voltages . . . . . . . . . . . . . . . . . .108
4.7 Signal flow graph of an FIR filter with N D M C 1 taps . . . . . . . . . . . . . . . .108
4.8 The layout of STSCL buffer/inverter gates with different
driving strengths in CMOS 0.18m [2–5]. To scale the
driving strength of a cell, number of parallel PMOS loads
needs to be increased proportional to the driving strength.
Also, the number of series NMOS tail bias transistors
needs to be reduced up to driving strength of 4, and then
for higher current driving, the number of parallel NMOS
devices needs to be increased .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4.9 The layout of the proposed FIR filter implemented in
CMOS 0.18m technology based on STSCL and CMOS topologies.. .110
4.10 (a) Simulated power consumption versus operation
frequency of the STSCL and the CMOS FIR filters
in 0.18m CMOS. Dashed lines are representing the
estimated power consumption based on the methodology
introduced in Chaps. 2 and 5. Here, the supply voltage of
STSCL circuit is set to be 0.5V. (b) Simulated leakage
current of the CMOS FIR filter in different supply voltage values . . . . . .111
4.11 Layout of AND2, full adder (FA), and XOR2 (from left to
right) implemented in CMOS 90 nm. The same cell is used
for different driving capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
4.12 Layout of the proposed FIR filter implemented in CMOS
90 nm using STSCL (left), and CMOS (right) topologies .. . . . . . . . . . . . . . .112
5.1 Simulated turn-on to turn-off current ratio ( D ION=IOFF)
of a static CMOS inverter gate implemented in 65-nm
CMOS technology in different corner cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
5.2 (a) A chain of CMOS gates with logic depth of N.
(b) Current drawn from supply source by one of the gates. . . . . . . . . . . . . . .119
5.3 Power consumption of a chain of CMOS gates versus
activity rate (˛) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
5.4 Variation of the critical activity rate (˛C ) as a function of
VDD for different technology nodes.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
5.5 Peak current and leakage current of a CMOS inverter gate
as a function of VDD in 65-nm technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
List of Figures xix
5.6 (a) Simulated power consumption versus operation
frequency for CMOS and STSCL XOR gates with logic
depth of N D 20. Note that CMOS power consumption
cannot be reduced beyond a certain level due to leakage.
(b) Maximum logic depth for which STSCL topology
exhibits less power consumption compared to the CMOS
topology based on (5.9) (dashed lines) in comparison to
the simulation results. The results are shown for both low
VT (top) and high VT devices (bottom) in 65-nm CMOS
technology. XOR logic gates are used for this comparison.
Here, VDD;STSCL D 400mV and VSW D 200mV . . . . . . . . . . . . . . . . . . . . . . . . .122
5.7 Measured power consumption versus operating frequency
for two (88) STSCL and CMOS array multipliers. The
simulations for both topologies are plotted for different
process corners and temperatures.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
5.8 (a) Compound STSCL gate (AND operation followed by
XOR gate). (b) Performance improvement in an (88)
multiplier circuit using compound STSCL gates . . . . . . . . . . . . . . . . . . . . . . . . .124
5.9 (a) Generic STSCL gate uses source follower buffer at the
output (SCLSFB) to improve the power–delay product of
the gate. (b) Design of standard library cells with different
driving strengths based on SCLSFB topology. CM stands
for the total parasitic capacitance seen by each output node
of the STSCL core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.10 (a) Total delay improvement using source-follower buffer
at the output of STSCL circuit in equal total power
consumption based on transistor level simulations. Data
points with a delay ratio of larger than unity represent
delay improvement (reduction). (b) Transient simulation
results: output waveforms (top) and supply current
(bottom) for an SCLSFB topology (ISS D 10 nA).
(c) Delay reduction (d ) for different I values compared
to the d;Max calculated based on (5.20) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.11 Pipelining technique for improving the activity rate in
STSCL topology. (a) Single stage pipelined gate and
timing diagram. (b) Multi-stage pipelined logic . . . . . . . . . . . . . . . . . . . . . . . . . .131
5.12 (a) STSCL full adder and keeper stage. Here, the tail
current bias VBN is switched according to CK (or CK)
while VBN0 is kept as a constant bias. (b) Simulated
output of the pipelined FA chain showing the holding and
tracking modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
xx List of Figures
5.13 (a) Photomicrograph of the test chip implemented
in 0.18-m technology. (b) Measured oscillation
frequency of STSCL ring oscillator in comparison to the
simulation results at different temperatures. (c) Total delay
improvement for total bias current per stage of 1 nA and
10 nA. Each ring oscillator is constructed of 8 delay cells.
Data points with a delay ratio of larger than unity represent
delay improvement (reduction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
5.14 (a) Test chip photomicrograph. Measured output of
the pipelined full adder chain in comparison to the
(b) input data and (c) reference clock. Here, VDD D 1 V,
VSW D 0:2 V, ISS D 1 nA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
5.15 (a) Measured delay versus tail bias current: total delay
of simple adder chain and stage delay in pipelined adder
chain. In both cases, the delay figure corresponds to the
time period between two consecutive inputs. The effective
operating frequency improves by a factor of 14 with
pipelining. (b) Measured power–delay product for the two
adder topologies. The pipelined adder topology achieves
a very significant reduction of PDP, over a wide range of
operating frequencies. (c) Power–frequency improvement
achieved by pipelining technique .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
5.16 (a) Section of the parallel multiplier where the signal flow
is regulated using two-phase micro-pipelining technique
for improving the performance of SCL gates. Note that
every FA stage output is followed by a keeper/latch
stage. (b) Eye diagram of the output of the multiplier
circuit. This plot shows the output after SCL-to-CMOS
level converter circuit. Input is a 27 1 pseudo random
bit stream (PRBS). Here, the period of input data is
Tp D1:5 s, ISS D10 nA, and ISS;L D100 pA; i.e., the
keeper stages dissipate only 1% of the power dissipated by
the FA stages. (c) Power–frequency improvement that can
be achieved in the (88) carry-save multiplier circuit, by
using shallow pipelining with keeper-latch stages . . . . . . . . . . . . . . . . . . . . . . . .137
6.1 Simulated power consumption of a chain of gates in 65-nm
CMOS technology based on static CMOS (solid line) and
STSCL topologies (dashed line). Variation of the power
consumption due to the process corners and temperature
variation is shown with standard-VT (a) and high-VT (b)
CMOS. Operating conditions: VDD.CMOS/ D 300mV and
VDD.STSCL/ D400mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
List of Figures xxi
6.2 (a) Conventional 6 transistor SRAM cell and (b) leakage
paths in this configuration. (c) 10T SRAMfor subthreshold
operation [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6.3 Schmitt trigger based SRAM bitcell introduced in [17]
operating at VDD D 160mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
6.4 (a) Schematic of a STSCL inverter. (b) The core of
the proposed memory cell based on STSCL topology.
(c) Completed memory cell. In this schematic, M10 is
shared among all the memory cells on a word line to save area . . . . . . . . .150
6.5 (a) Circuit schematic, and (b) timing diagram of the
STSCL-based SRAM cell. (c) Simulated butterfly curve of
a cell in CMOS 65 nm (showing different corner cases) for
VDD D 500mV and VSW D 200mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
6.6 Sense amplifier used to reconstruct the data at the output
of memory cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
6.7 Leakage detector and bias current generator circuit schematic . . . . . . . . . .153
6.8 The chip photomicrograph of the ultra low stand-by
(leakage) current SRAM array (1 kb block) fabricated with
conventional 0.18-m CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
6.9 Measured (a) butterfly curves and (b) statistical
distribution of the SNM, for the proposed SRAM cell
(ICORE D 10 pA, VSW D 200mV, and VDD D 500mV) . . . . . . . . . . . . . . . . . .154
6.10 Measured variation of the SNM versus VSW (for
ICORE D 10 pA) and variations of SNM versus tail bias
current (ICORE) for VSW D 200mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
6.11 Variation of the idle power consumption (per cell) versus
operating frequency, comparing this work with the SRAM
cell presented in [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
7.1 A conceptual block diagram of a widely adjustable
mixed-mode integrated circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
7.2 (a) Simplified replica bias circuit. (b) Conventional folded
cascode amplifier circuit topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
7.3 Modified current mirror schematic to be used in very low
bias current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
7.4 (a) Circuit schematic of the amplifier. (b) Simulated
unity gain bandwidth (UGBW) and phase margin of the
amplifier for different current bias values. In this plot,
IC is the reference current value used to change the filter
cutoff frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
xxii List of Figures
7.5 (a) Single stage differential operational transconductance
amplifier (OTA) can be used as a widely adjustable
transconductor. Typical I/V characteristics of the
differential pair OTA also is shown. (b) Maximum voltage
swing at the input of differential pair OTA to have a
nonlinearity less than 5% at the output current (nominal
.W=L/ D 1:0m/0.4m) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
7.6 Biquadratic gm-C filter: (a) conventional topology and
(b) modified topology with improved linearity performance.. . . . . . . . . . . .168
7.7 Comparing the linearity performance of the two
biquadratic filters shown in Fig. 7.6 based on behavioral
modeling. Here, it is assumed that the input differential
pair transistors are biased in subthreshold regime and
transconductance can be calculated using (7.15) . . . . . . . . . . . . . . . . . . . . . . . . .169
7.8 Linearized transconductance suitable for wide tuning
range applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
7.9 Tunable active-RC (MOSFET-C) filter using a variable
resistor. The power consumption of the amplifier is
scalable with respect to the filter cutoff frequency.. . . . . . . . . . . . . . . . . . . . . . .172
7.10 High-valued resistance implementation based on
subthreshold PMOS device: (a) conventional PMOS
device and its I/V characteristics, (b) proposed PMOS
device and its I/V characteristics with extended linearity
range [9], (c) I/V characteristics of the devices shown
in (a) and (b). (d) Measured I/V characteristics of the
proposed floating resistor for VSD < 0V, and VSD > 0V. . . . . . . . . . . . . . . . .173
7.11 Proposed floating resistance: (a) circuit schematic,
(b) measured I/V characteristics of the proposed
configuration for different VC values, and
(c) measured resistance of the proposed
floating resistor with respect to the gate-source
voltage of MN (VC D VGS;MN D VSG;MP1;2).
Here, .W=L/pMOS D 0:24 m=0:40 m and
.W=L/nMOS D 1:0 m=0:40 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
7.12 High-valued floating resistance with improved linearity . . . . . . . . . . . . . . . . .175
7.13 Extreme high-valued resistance using negative VSG values . . . . . . . . . . . . . .176
7.14 A second order MOSFET-C filter. All the resistors are
implemented using the proposed floating resistor shown in
Fig. 7.11a. Quality factor of this filter can be tuned through
R2 independent to the cutoff frequency. In this design,
R1 D R3 D R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
7.15 Chip photomicrograph of the proposed filters implemented
in 0.18m CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
List of Figures xxiii
7.16 Measured MOSFET-C filter characteristics: (a) frequency
transfer characteristics. (b) cutoff frequency versus tuning
current in comparison to the simulation results, and
(c) Q tuning by changing R2 value at IC D 1 nA. . . . . . . . . . . . . . . . . . . . . . . .179
7.17 Measured (a) third order intermodulation intercept point
and (b) noise of the proposed MOSFET-C filter . . . . . . . . . . . . . . . . . . . . . . . . . .180
7.18 Measured gm-C filter characteristics: (a) frequency
transfer characteristics and (b) cutoff frequency versus
tuning current in comparison to the simulation results . . . . . . . . . . . . . . . . . . .181
7.19 Measured: (a) third order intermodulation intercept
point (IP3) and (b) noise of the proposed gm-C, for
different filter cutoff frequencies. (c) Third order harmonic
distortion (HD3) of the proposed gm-C filter in comparison
the conventional topology when IC D 1 nA, and fin D fc=4 . . . . . . . . . . .181
7.20 FOM comparison to some other reports versus normalized
filter area (area is normalized to the order of the filter). The
data points used in this figure are extracted from [11] and [12] .. . . . . . . . .183
8.1 Topology of a SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
8.2 Topology of a FAI ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
8.3 Performance improvement of the reported FAI ADCs
versus time and technology nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
8.4 Ideal resistor ladder to generate reference voltages . . . . . . . . . . . . . . . . . . . . . . .193
8.5 (a) INL degradation due to the mismatch on resistors
of reference voltage ladder simulated in MATLAB.
(b) ˛Ladder as a function of ADC resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
8.6 Differential pair based pre-amplifier and comparator:
(a) pre-amplifier, (b) a comparator consisting of
pre-amplification and latch stages, and (c) a simple model
for the proposed three stage circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
8.7 Comparator offset effect on INL of the ADC deduced
fromMATLAB behavioral modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
8.8 Minimum achievable FOM using flash topology for ADC
based on behavioral modeling. This figure also shows the
power consumption (excluding encoder part) and the total
input capacitance of the ADC as a function of Nb . . . . . . . . . . . . . . . . . . . . . . . .199
8.9 Folding scheme: four folders are used to generate four
folded signals. Each two consecutive folded signals can be
used to generate interpolated signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
8.10 Sample folder circuit (NF D 3) uses nonlinear transconductors . . . . . . . .200
8.11 (a) Current mode interpolator. (b) Merged folder and
interpolator stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
8.12 Inherent INL of a current-mode interpolator biased in
subthreshold regime .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
xxiv List of Figures
8.13 Low power resistor ladder implementation: (a) ideal
resistor ladder used to generate reference voltages,
(b) high-value resistance based on subthreshold PMOS
device, (c) biasing the proposed high-value resistance
where the resistivity can be adjusted through IRES, and
(d) compact resistor ladder sharing the same biasing
circuitry for more than one resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
8.14 (a) High valued load resistance. (b) Decoupling
the parasitic capacitance of the well-substrate from
output node. (c) Subthreshold pre-amplifier stage. (d)
Improvement of frequency response through parasitic
capacitance decoupling.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.15 Error correction and encoder using pipelined STSCL
topology. Waveforms of the bit synchronization block.
MSB, MSB1, andMSB2 are the outputs. C00 is the
synchronization bit and CP1–CP8 are cycle pointers . . . . . . . . . . . . . . . . . . . . .206
8.16 Democratic cell and its layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
8.17 Cyclical code to binary code converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
8.18 Control of power consumption with respect to the
operating frequency in the proposed subthreshold
source-coupled FAI ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
8.19 Maximum operation frequency of the
digital section as a function of tail bias
current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
8.20 Photomicrograph of the proposed chip implemented in
0.18-m CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
8.21 Measured differential non-linearity (DNL) and integral
non-linearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
9.1 First order † modulator topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
9.2 Timing operation of a ring oscillator based quantizer (ROQ) . . . . . . . . . . . .217
9.3 (a) STSCL delay cell and replica bias circuit to generate
bias voltage for PMOS and NMOS transistors. (b) Sample
differential ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
9.4 Implementation of ring oscillator based quantizer without
the need to counter as proposed in [6]. The topology is
modified to make it suitable for scalable DR ADCs . . . . . . . . . . . . . . . . . . . . . .221
9.5 (a) SNDR versus input signal amplitude based on
behavioral modeling of a first order R† in MATLAB
(here: Nd D 15, and OSR D 64). (b) SNDR versus
number of delay elements in the ring oscillator
(here: Ain=0:5, andOSR D 64) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
9.6 The effect of sampling clock jitter on SNDR based on
behavioral modeling in MATLAB for a first order R† modulator . . . .225
9.7 Sampling the output of ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
List of Figures xxv
9.8 SNDR of a first order quantizer when: OSC D 0:001td ,
CK D 0:001Ts, and td D 0:01td . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
9.9 Effect of delay mismatch on first order quantizer based on
behavioral modeling inMATLAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
9.10 Effect of oscillator jitter on first order quantizer based on
behavioral modeling inMATLAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
9.11 A slice of the circuit showing part of ring oscillator and
digital part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
9.12 Schematic of a companding current-mode integrator
adopted from [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
9.13 Circuit diagram of the current steering DAC and
differential current-mode integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
9.14 Discrete-time and continuous-time † modulators .. . . . . . . . . . . . . . . . . . . . .234
9.15 Block diagram of a third order R† modulator: (a) based
on DT integrators, (b) based on CT integrators. (c) Model
of a ROQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
9.16 Performance of a third order R† based on behavioral
modeling in MATLAB: (a) Effect of sampling clock
jitter on SNDR. (b) Effect of leaky integrator on SNDR.
(c) Effect of DAC component mismatch on SNDR, with
and without DWA. (d) Effect of delay element mismatch
on SNR and SNDR. (e) Effect of ring oscillator jitter on
system performance. (f) SNR and SNDR of the system
including all nonideal effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
9.17 (a) Chip phot and mask layout of the test chip fabricated in
90-nm CMOS technology. (b) Mask layout of the quantizer circuit . . . . .240
9.18 Simulated supply current consumption of the R†
modulator for ISS.nom/ D 1 nA. The variation on supply
current is about 15% of the total circuit current consumption . . . . . . . . . . .241
9.19 Measurement results in different sampling frequencies:
(a) SNR and SNDR values and (b) Power dissipation of
the modulator. Here: OSRD64, AIN D 20 dB, VDD D 1:2V. . . . . . . . . .241
10.1 Conventional charge-pump PLL (CPLL) topology .. . . . . . . . . . . . . . . . . . . . . .244
10.2 Charge pump circuit with programmable bias current.. . . . . . . . . . . . . . . . . . .248
10.3 (a) Transient loop response to the variation at the input
frequency of the PLL. (b) The effect of small loop filter
bandwidth with discarding the desirable component at the
output of PFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
10.4 Topology of the proposed self-biased adaptive bandwidth PLL . . . . . . . . .251
10.5 Current-controlled ring oscillator structure uses STSCL
cells as delay stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
10.6 Simulated tuning range of STSCL ring oscillator with 8
and 24 delay elements designed in 0.13-m CMOS technology .. . . . . . .253
xxvi List of Figures
10.7 Frequency divider circuit: (a) STSCL latch circuit
schematic and (b) Frequency divider .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
10.8 (a) Wide swing transconductor. (b) I–V characteristics of
the transconductor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
10.9 Simulated transient response of the PLL in different frequencies . . . . . . .255
10.10 Simulated transient response of the PLL when there is a
jump at the input frequency. In this simulation, the initial
input frequency is f1 D 1:12MHz and then there is a jump
to f2 D f1=200 D 5:6 kHz. At the end of simulation,
again there is a jump back to f1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
10.11 Mask layout of the proposed wide tuning range PLL
implemented in 0.13-m CMOS technology and
occupying 300m 200m area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
10.12 Measured rms supply current consumption versus
oscillation frequency for two different loop-divider values . . . . . . . . . . . . . .257
学习学习~谢谢了~
拜读一下，多谢楼主分享。
在那里？学习学习!呵呵！谢谢！
学习学习~谢谢了~
这个得学习学习
good book need to have a look
vDSbfb你放哪的你个股份个备份表
Extreme Low-Power Mixed Signal IC Design: Extreme Low-Power Mixed Signal IC Design.pdf
