ESD Design and Synthesis_[Steven H. Voldman][Wiley][2011][290P].pdf

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About the Author xv
Preface xvii
Acknowledgments xix
1 ESD Design Synthesis 1
1.1 ESD Design Synthesis and Architecture Flow 1
1.1.1 Top-Down ESD Design 2
1.1.2 Bottom-Up ESD Design 2
1.1.3 Top-Down ESD Design – Memory Semiconductor Chips 3
1.1.4 Top-Down ESD Design – ASIC Design System 3
1.2 ESD Design – The Signal Path and the Alternate Current Path 4
1.3 ESD Electrical Circuit and Schematic Architecture Concepts 6
1.3.1 The Ideal ESD Network and the Current–Voltage DC Design Window 6
1.3.2 The ESD Design Window 7
1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window 9
1.4 Mapping Semiconductor Chips and ESD Designs 11
1.4.1 Mapping Across Semiconductor Fabricators 11
1.4.2 ESD Design Mapping Across Technology Generations 13
1.4.3 Mapping from Bipolar Technology to CMOS Technology 14
1.4.4 Mapping from Digital CMOS Technology to Mixed Signal
Analog–Digital CMOS Technology 15
1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) 15
1.4.6 ESD Design – Mapping CMOS to RF CMOS Technology 16
1.5 ESD Chip Architecture and ESD Test Standards 17
1.5.1 ESD Chip Architecture and ESD Testing 17
1.6 ESD Testing 17
1.6.1 ESD Qualification Testing 18
1.6.2 ESD Test Models 18
1.6.3 ESD Characterization Testing 19
1.6.4 TLP Testing 19
1.7 ESD Chip Architecture and ESD Alternative Current Paths 21
1.7.1 ESD Circuits, I/O, and Cores 21
1.7.2 ESD Signal Pin Circuits 21
1.7.3 ESD Power Clamp Networks 23
1.7.4 ESD Rail-to-Rail Circuits 24
1.7.5 ESD Design and Noise 25
1.7.6 Internal Signal Path ESD Networks 27
1.7.7 Cross-Domain ESD Networks 28
1.8 ESD Networks, Sequencing, and Chip Architecture 28
1.9 ESD Design Synthesis – Latchup-Free ESD Networks 29
1.10 ESD Design Concepts – Buffering – Inter-Device 31
1.11 ESD Design Concepts – Ballasting – Inter-Device 32
1.12 ESD Design Concepts – Ballasting – Intra-Device 34
1.13 ESD Design Concepts – Distributed Load Techniques 34
1.14 ESD Design Concepts – Dummy Circuits 35
1.15 ESD Design Concepts – Power Supply De-Coupling 36
1.16 ESD Design Concepts – Feedback Loop De-Coupling 36
1.17 ESD Layout and Floorplan-Related Concepts 37
1.17.1 Design Symmetry 37
1.17.2 Design Segmentation 38
1.17.3 ESD Design Concepts – Utilization of Empty Space 39
1.17.4 ESD Design Synthesis – Across Chip Line Width Variation (ACLV) 40
1.17.5 ESD Design Concepts – Dummy Shapes 42
1.17.6 ESD Design Concepts – Dummy Masks 42
1.17.7 ESD Design Concepts – Adjacency 43
1.18 ESD Design Concepts – Analog Circuit Techniques 43
1.19 ESD Design Concepts – Wire Bonds 44
1.20 Design Rules 45
1.20.1 ESD Design Rule Checking (DRC) 45
1.20.2 ESD Layout vs. Schematic (LVS) 45
1.20.3 Electrical Resistance Checking (ERC) 46
1.21 Summary and Closing Comments 46
Problems 46
References 47
2 ESD Architecture and Floorplanning 53
2.1 ESD Design Floorplan 53
2.2 Peripheral I/O Design 54
2.2.1 Pad-Limited Peripheral I/O Design Architecture 55
2.2.2 Pad-Limited Peripheral I/O Design Architecture – Staggered I/O 56
2.2.3 Core-Limited Peripheral I/O Design Architecture 57
2.3 Lumped ESD Power Clamp in Peripheral I/O Design Architecture 58
2.3.1 Lumped ESD Power Clamp in Peripheral I/O Design Architecture
in the Semiconductor Chip Corners 58
2.3.2 Lumped ESD Power Clamp in Peripheral I/O Design
Architecture – Power Pads 59
2.4 Lumped ESD Power Clamp in Peripheral I/O Design
Architecture – Master/Slave ESD Power Clamp System 60
2.5 Array I/O 61
viii CONTENTS
2.5.1 Array I/O – Off-Chip Driver Banks 62
2.5.2 Array I/O Nibble Architecture 64
2.5.3 Array I/O Pair Architecture 65
2.5.4 Array I/O – Fully Distributed 65
2.6 ESD Architecture – Dummy Bus Architectures 69
2.6.1 ESD Architecture – Dummy VDD Bus 69
2.6.2 ESD Architecture – Dummy Ground (VSS) Bus 70
2.7 Native Voltage Power Supply Architecture 71
2.7.1 Single Power Supply Architecture 71
2.8 Mixed-Voltage Architecture 72
2.8.1 Mixed-Voltage Architecture – Single Power Supply 72
2.8.2 Mixed-Voltage Architecture – Dual Power Supply 73
2.9 Mixed-Signal Architecture 76
2.9.1 Mixed-Signal Architecture – Bipolar 76
2.9.2 Mixed-Signal Architecture – CMOS 77
2.10 Mixed-System Architecture – Digital and Analog CMOS 78
2.10.1 Digital and Analog CMOS Architecture 78
2.10.2 Digital and Analog Floorplan – Placement of Analog Circuits 80
2.11 Mixed-Signal Architecture – Digital, Analog, and RF Architecture 81
2.12 Summary and Closing Comments 82
Problems 83
References 84
3 ESD Power Grid Design 87
3.1 ESD Power Grid 87
3.1.1 ESD Power Grid – Key ESD Design Parameters 87
3.1.2 ESD and the Alternative Current Path – The Role of
ESD Power Grid Resistance 88
3.2 Semiconductor Chip Impedance 91
3.3 Interconnect Failure and Dynamic On-Resistance 92
3.3.1 Interconnect Dynamic On-Resistance 92
3.3.2 Ti/Al/Ti Interconnect Failure 93
3.3.3 Copper Interconnect Failure 95
3.3.4 Melting Temperature of Interconnect Materials 96
3.4 Interconnect Wire and Via Guidelines 97
3.4.1 Interconnect Wire and Via Guidelines for HBM ESD Events 97
3.4.2 Interconnect Wire and Via Guidelines for MM ESD Events 98
3.4.3 Interconnect Wire and Via Guidelines for CDM ESD Events 98
3.4.4 Interconnect Wire and Via Guidelines for HMM and IEC
61000-4-2 ESD Events 99
3.4.5 Wire and Via ESD Metrics 99
3.5 ESD Power Grid Resistance 100
3.5.1 Power Grid Design – ESD Input to Power Grid Resistance 100
3.5.2 ESD Input to Power Grid Connections – Across ESD Bus Resistance 101
3.5.3 Power Grid Design – ESD Power Clamp to Power Grid
Resistance Evaluation 103
CONTENTS ix
3.5.4 Power Grid Design – Resistance Evaluation 104
3.5.5 Power Grid Design Distribution Representation 106
3.6 Power Grid Layout Design 108
3.6.1 Power Grid Design – Slotting of Power Grid 108
3.6.2 Power Grid Design – Segmentation of Power Grids 109
3.6.3 Power Grid Design – Chip Corners 110
3.6.4 Power Grid Design – Stacking of Metal Levels 111
3.6.5 Power Grid Design – Wiring Bays and Weaved Power Bus Designs 112
3.7 ESD Specification Power Grid Considerations 112
3.7.1 CDM Specification Power Grid and Interconnect Design
Considerations 112
3.7.2 HMM and IEC Specification Power Grid and Interconnect
Design Considerations 112
3.8 Power Grid Design Synthesis – ESD Design Rule Checking Methods 113
3.8.1 Power Grid Design Synthesis – ESD DRC Methods Using an
ESD Virtual Design Level 113
3.8.2 Power Grid Design Synthesis – ESD DRC Methods Using
an ESD Interconnect Parameterized Cell 115
3.9 Summary and Closing Comments 118
Problems 119
References 120
4 ESD Power Clamps 123
4.1 ESD Power Clamps 123
4.1.1 Classification of ESD Power Clamps 123
4.1.2 Design Synthesis of ESD Power Clamp – Key Design Parameters 125
4.2 Design Synthesis of ESD Power Clamps 125
4.2.1 Transient Response Frequency Trigger Element and the
ESD Frequency Window 126
4.2.2 The ESD Power Clamp Frequency Design Window 126
4.2.3 Design Synthesis of ESD Power Clamp – Voltage Triggered
ESD Trigger Elements 127
4.3 Design Synthesis of ESD Power Clamp – The ESD Power
Clamp Shunting Element 128
4.3.1 ESD Power Clamp Trigger Condition vs. Shunt Failure 129
4.3.2 ESD Clamp Element – Width Scaling 130
4.3.3 ESD Clamp Element – On-Resistance 130
4.3.4 ESD Clamp Element – Safe Operating Area 131
4.4 ESD Power Clamp Issues 131
4.4.1 ESD Power Clamp Issues – Power-Up and Power-Down 131
4.4.2 ESD Power Clamp Issues – False Triggering 131
4.4.3 ESD Power Clamp Issues – Pre-Charging 132
4.4.4 ESD Power Clamp Issues – Post-Charging 132
4.5 ESD Power Clamp Design 132
4.5.1 Native Power Supply RC-Triggered MOSFET ESD Power Clamp 132
x CONTENTS
4.5.2 Non-Native Power Supply RC-Triggered MOSFET ESD
Power Clamp 133
4.5.3 ESD Power Clamp Networks with Improved Inverter
Stage Feedback 134
4.5.4 ESD Power Clamp Design Synthesis – Forward Bias Triggered
ESD Power Clamps 136
4.5.5 ESD Power Clamp Design Synthesis – IEC 61000-4-2
Responsive ESD Power Clamps 136
4.5.6 ESD Power Clamp Design Synthesis – Pre-Charging and
Post-Charging Insensitive ESD Power Clamps 137
4.6 ESD Power Clamp Design Synthesis – Bipolar ESD Power Clamps 137
4.6.1 Bipolar ESD Power Clamps with Zener Breakdown
Trigger Element 138
4.6.2 Bipolar ESD Power Clamps with Bipolar Transistor BVCEO
Breakdown Trigger Element 138
4.6.3 Bipolar ESD Power Clamps with BVCEO Bipolar Transistor
Trigger and Variable Trigger Diode String Network 140
4.6.4 Bipolar ESD Power Clamps with Frequency Trigger Elements 141
4.7 Master/Slave ESD Power Clamp Systems 141
4.8 Summary and Closing Comments 143
Problems 143
References 144
5 ESD Signal Pin Networks Design and Synthesis 149
5.1 ESD Signal Pin Structures 149
5.1.1 Classification of ESD Signal Pin Networks 150
5.1.2 ESD Design Synthesis of ESD Signal Devices – Key Design
Parameters 151
5.2 ESD Input Structures – ESD and Bond Pads Layout 152
5.2.1 ESD and Bond Pad Layout and Synthesis 152
5.2.2 ESD Structures Between Bond Pads 153
5.2.3 Split I/O and Bond Pad 154
5.2.4 Split ESD Adjacent to Bond Pad 155
5.2.5 ESD Structures Partially Under Bond Pads 157
5.2.6 ESD Structures Under and Between the Bond Pads 158
5.2.7 ESD Circuits and RF Bond Pad Integration 158
5.2.8 RF ESD Signal Pad Structures Under Bond Pads 161
5.3 ESD Design Synthesis and Layout of MOSFETs 163
5.3.1 MOSFET Key Design Parameters 163
5.3.2 Single MOSFET with Silicide Block Masks 166
5.3.3 Series Cascode MOSFET 167
5.3.4 Triple-well MOSFETs 168
5.4 ESD Design Synthesis and Layout of Diodes 169
5.4.1 ESD Diode Key Design Parameters 169
5.4.2 ESD Design Synthesis of Dual-Diode Networks 170
5.4.3 ESD Design Synthesis of Diode String Networks 172
CONTENTS xi
5.4.4 ESD Design Synthesis of Back-to-Back Diode String 173
5.4.5 ESD Design Synthesis for Differential Pair 174
5.5 ESD Design Synthesis of SCRs 175
5.5.1 ESD Design Synthesis of Uni-directional SCRs 177
5.5.2 ESD Design Synthesis of Bi-directional SCRs 178
5.5.3 ESD Design Synthesis of SCRs – External Trigger Element 180
5.6 ESD Design Synthesis and Layout of Resistors 180
5.6.1 Polysilicon Resistor Design Layout 180
5.6.2 Diffusion Resistor Design Layout 181
5.6.3 P-diffusion Resistor Design Layout 181
5.6.4 N-diffusion Resistor Design 183
5.6.5 Buried Resistors 184
5.6.6 N-well Resistors 185
5.7 ESD Design Synthesis of Inductors 187
5.8 Summary and Closing Comments 188
Problems 188
References 190
6 Guard Ring Design and Synthesis 193
6.1 Guard Ring Design and Integration 193
6.2 Guard Ring Characterization 194
6.2.1 Guard Ring Efficiency 194
6.2.2 Guard Ring Theory – A Generalized Bipolar Transistor Perspective 196
6.2.3 Guard Ring Theory – A Probability of Escape Perspective 196
6.2.4 Guard Ring – The Injection Ratio 197
6.3 Semiconductor Chip Guard Ring Seal 198
6.4 I/O to Core Guard Rings 199
6.5 I/O to I/O Guard Rings 200
6.6 Within I/O Guard Rings 201
6.6.1 Within I/O Cell Guard Ring 201
6.6.2 ESD-to-I/O OCD Guard Ring 201
6.7 ESD Signal Pin Guard Rings 202
6.7.1 ESD Signal Pin Guard Rings and Dual-Diode ESD Network 204
6.8 Library Element Guard Rings 205
6.8.1 N-channel MOSFET Guard Rings 205
6.8.2 P-channel MOSFET Guard Rings 208
6.8.3 RF Guard Rings 210
6.9 Mixed-Signal Guard Rings – Digital to Analog 210
6.10 Mixed-Voltage Guard Rings – High Voltage to Low Voltage 211
6.10.1 Guard Rings – High Voltage 212
6.11 Passive and Active Guard Rings 213
6.11.1 Passive Guard Rings 213
6.11.2 Active Guard Rings 214
6.12 Trench Guard Rings 215
6.13 TSV Guard Rings 216
6.14 Guard Ring DRC 218
xii CONTENTS
6.14.1 Internal Latchup and Guard Ring Design Rules 219
6.14.2 External Latchup Guard Ring Design Rules 219
6.15 Guard Rings and Computer Aided Design Methods 220
6.15.1 Built-in Guard Rings 220
6.15.2 Guard Ring Parameterized Cells 221
6.15.3 Guard Ring p-Cell SKILL Code 223
6.15.4 Guard Ring Resistance CAD Design Checking 229
6.15.5 Post-Processing Methodology of Guard Ring Modification 231
6.16 Summary and Closing Comments 232
Problems 232
References 234
7 ESD Full-Chip Design Integration and Architecture 239
7.1 Design Synthesis and Integration 239
7.2 Digital Design 239
7.3 Custom Design vs. Standard Cell Design 240
7.4 Memory ESD Design 240
7.4.1 DRAM Design 240
7.4.2 SRAM Design 244
7.4.3 Non-Volatile RAM ESD Design 246
7.5 Microprocessor ESD Design 247
7.5.1 3.3 V Microprocessor with 5.0 V to 3.3 V Interface 247
7.5.2 2.5 V Microprocessor with 5.0 V to 2.5 V Interface 249
7.5.3 1.8 V Microprocessor with 3.3 V to 1.8 V Interface 249
7.6 Application-Specific Integrated Circuits 250
7.6.1 ASIC ESD Design 250
7.6.2 ASIC Design Gate Array Standard Cell I/O 251
7.6.3 ASIC Design System with Multiple Power Rails 252
7.6.4 ASIC Design System with Voltage Islands 252
7.7 CMOS Image Processing Chip Design 254
7.7.1 CMOS Image Processing Chip Design with Long/Narrow
Standard Cell 255
7.7.2 CMOS Image Processing Chip Design with Short/Wide
Standard Cell 256
7.8 Mixed-Signal Architecture 257
7.8.1 Mixed-Signal Architecture – Digital and Analog 257
7.8.2 Mixed-Signal Architecture – Digital, Analog, and RF 258
7.9 Summary and Closing Comments 259
Problems 260
References 261
Index 265

:19bb:49bb

thanks

About the Author xv
Preface xvii
Acknowledgments xix
1 ESD Design Synthesis

ESD Design and Synthesis

多谢楼主。

多谢楼主。

多谢楼主。

have to take a look

:16bb:46bb:48bb

学习一下了。

现在正在看ESD，也在处理ESD

看看，静电方面的资料

非常感谢楼主 好书1

多谢楼主分享，好东西啊

感謝大大分享這麼珍貴的資料~希望對ESD有更深入了解3Q

学习  学习‘’‘’‘’‘’‘’‘’‘’‘’

很不错的教程，多谢啊！

谢谢楼主{:soso_e179:}

kankan...............

最近公司 esd一堆問題~~~ 正好可以學習,感恩分享 ^^~

非常感谢楼主，多谢分享

looks great

好动额呵呵呵