Complete.PCB.Design.Using.OrCad.Capture.and.Layout.(Apr.2007).part18.rar

CHAPTER 1. INTRODUCTION TO CAD AND PCB FABRICATION
COMPUTER AIDED DESIGN AND THE ORCAD DESIGN SUITE
PRINTED CIRCUIT BOARD FABRICATION
    PCB cores and layer stack-up
    PCB fabrication process
    Photolithography and chemical etching
    Mechanical milling
    Layer registration
FUNCTION OF ORCAD LAYOUT IN THE PCB DESIGN PROCESS
DESIGN FILES CREATED BY LAYOUT
    Layout format files (.MAX)
    Post process (Gerber) files
    PCB assembly layers and files

CHAPTER 2. INTRODUCTION TO THE PCB DESIGN FLOW BY EXAMPLE
OVERVIEW OF THE DESIGN FLOW
CREATING A CIRCUIT DESIGN WITH CAPTURE
    Starting a New Project
    Placing Parts
    Wiring (Connecting) the Parts
    Creating the Layout Netlist in Capture
DESIGNING THE PCB WITH LAYOUT
    Starting Layout and Importing the Netlist
    Making a Board Outline
    Placing the Parts
    Autorouting the Board
    Manual Routing
    Clean-up
    Locking Traces
    Performing a Design Rule Check (DRC)
    Post Processing the Board Design for Manufacturing

CHAPTER 3. PROJECT STRUCTURES AND THE LAYOUT TOOLSET
PROJECT SETUP AND SCHEMATIC ENTRY DETAILS
    Capture Projects Explained
    Capture Part Libraries explained
UNDERSTANDING THE LAYOUT ENVIRONMENT AND TOOLSET
    Board Technology Files
    The AutoECO Utility
    The Session Frame and Design Windows
    The Tool Bar
    Controlling the Autorouter
    Post Processing and Layer Details

CHAPTER 4. INTRODUCTION TO INDUSTRY STANDARDS
INTRODUCTION TO THE STANDARDS ORGANIZATIONS
    Institute for Printed Circuits (IPC)
    Electronic Industries Alliance (EIA)
    Joint Electron Device Engineering Council (JEDEC)
    International Engineering Consortium (IEC)
    Military Standards (MIL-STD)
    American National Standards Institute (ANSI)
    Institute of Electrical and Electronics Engineers (IEEE)
CLASSES AND TYPES OF PCBS
    Performance Classes
    Producibility Levels
    Fabrication types and Assembly subclasses
    OrCAD Layout Design Domplexity Levels—IPC Performance Classes
    IPC Land Pattern Density Levels
INTRODUCTION TO STANDARD FABRICATION ALLOWANCES (SFA)
    Registration tolerances
    Breakout and annular ring control
PCB DIMENSIONS AND TOLERANCES
    Standard panel sizes
    Tooling area allowances and effective panel usage
    Standard Finished PCB Thickness
    Core Thickness
    Prepreg Thickness
    Copper thickness for PTHs and vias
    Copper cladding/foil thickness
COPPER TRACE AND ETCHING TOLERANCES
STANDARD HOLE DIMENSIONS
Aspect ratio (hole size to PCB thickness)
SOLDERMASK TOLERANCE

CHAPTER 5. PCB DESIGN FOR MANUFACTURABILITY
INTRODUCTION TO PCB ASSEMBLY AND SOLDERING PROCESSES
ASSEMBLY PROCESSES
    Manual Assembly Processes
    Automated Assembly Processes (Pick and Place)
SOLDERING PROCESSES
    Manual Soldering
    Wave Soldering
    Reflow Soldering
COMPONENT PLACEMENT AND ORIENTATION GUIDE
    General Considerations
COMPONENT SPACING FOR THROUGH-HOLE DEVICES (THDS)
    Discrete THDs
    Integrated circuit through-hole devices
    Mixed discrete and IC through-hole devices
    Holes and jumper wires
COMPONENT SPACING FOR SURFACE MOUNTED DEVICES (SMDS)
    Discrete SMDs
    Integrated circuit SMDs
    Mixed discrete and IC SMDs
MIXED THD AND SMD SPACING REQUIREMENTS
FOOTPRINT AND PADSTACK DESIGN FOR PCB MANUFACTURABILITY
LAND PATTERNS FOR SURFACE MOUNTED DEVICES (SMD)
    SMD Padstack Design
    SMD Footprint Design
LAND PATTERNS FOR THROUGH-HOLE DEVICES (THD)
    Footprint design for through-hole devices
    Padstack design for through-hole devices
    Hole to lead ratio
    PTH land dimension (annular ring width)
    Clearance between Plane layers and PTHs
    Soldermask and solder paste dimensions

CHAPTER 6. PCB DESIGN FOR SIGNAL INTEGRITY
CIRCUIT DESIGN ISSUES VS. PCB DESIGN ISSUES
    Noise
    Distortion
    Frequency response
ELECTROMAGNETIC INTERFERENCE AND CROSSTALK
    Magnetic fields and inductive coupling
    Loop inductance
    Electric fields and Capacitive Coupling
GROUND PLANES, AND GROUND BOUNCE
    What ground is and what it is not
    Ground (return) planes
PCB ELECTRICAL CHARACTERISTICS
    Characteristic Impedance
    ReflectionsRinging
    Electrically long traces
    Critical length
    Transmission line terminations
PCB ROUTING TOPICS
    Parts placement for Electrical considerations
    PCB layer stackup
    Bypass capacitors and fanout
    Trace width for current carrying capability
    Trace width for characteristic impedance
    Trace spacing for Voltage withstanding
    Trace spacing to minimize crosstalk (3-W Rule)
    Traces with acute and 90° angles

CHAPTER 7. MAKING AND EDITING CAPTURE PARTS
THE CAPTURE PART LIBRARIES
TYPES OF PACKAGING
    Homogeneous parts
    Heterogeneous Parts
PINS
PART EDITING TOOLS
    The Select Tool and Settings
    The Pin Tools
    The Graphics Tools
    The Zoom Tools
CONSTRUCTING CAPTURE PARTS
    Methods of constructing new parts:
METHOD 1: CONSTRUCTING PARTS USING THE NEW PART OPTION (DESIGN MENU)
    Design example for a passive, homogeneous part
    Design example for an active, multi-part, homogeneous component
    Assigning power pin visibility
    Design example for a passive, heterogeneous part
METHOD 2: CONSTRUCTING PARTS WITH CAPTURE USING THE DESIGN SPREADSHEET
METHOD 3: CONSTRUCTING PARTS USING GENERATE PART FROM THE TOOLS MENU
METHOD 4: GENERATING PARTS WITH THE PSPICE MODEL EDITOR
    Making and/or obtaining new PSpice libraries for making new Capture parts
    Download libraries and/or models from the internet.
    Making a Capture part from a Capture schematic design
    Adding PSpice templates (models) to pre-existing Capture parts
CONSTRUCTING CAPTURE SYMOBLS

CHAPTER 8. MAKING AND EDITING LAYOUT FOOTPRINTS
INTRODUCTION TO THE LIBRARY MANGER
INTRODUCTION LAYOUT’S FOOTPRINT LIBRARIES AND NAMING CONVENTIONS
    Layout’s footprint libraries
    Naming conventions
THE COMPOSITION OF FOOTPRINTS
    Padstacks
    Obstacles
    Text
    Datums and insertion origins
THE BASIC FOOTPRINT DESIGN PROCESS
WORKING WITH PADSTACKS
    Accessing existing padstacks
    Editing padstack properties from the spreadsheet
    Saving footprints and padstacks
FOOTPRINT DESIGN EXAMPLES
    Design example 1: A surface mount footprint design
    Design example2: A modified through-hole footprint design example
USING THE PAD ARRAY GENERATOR
    Introduction
    Footprint Design for pin grid arrays (PGA)
    Footprint Design for ball grid arrays (BGA)
    Blind, buried, and micro vias
    Mounting holes
    Printing a Catalog of a footprint library

CHAPTER 9. PCB DESIGN EXAMPLES
OVERVIEW OF THE DESIGN FLOW
EXAMPLE 1: DUAL POWER SUPPLY, ANALOG DESIGN
    Initial design concept and preparation
PROJECT SETUP AND DESIGN IN CAPTURE
    Setting up the project
    Drawing the schematic with Capture
    Placing parts
    Connect parts with wires (signal nets)
    Making power and ground connections
    Preparing the design for Layout
    Grouping related components.
    Annotation
    Performing a schematic DRC in Capture
    Generating the Layout netlist (.MNL)
DEFINING THE BOARD REQUIREMENTS
    Specifying packaging and assembly requirements
    Defining the layer stack-up
    Determining trace width
    Determining trace spacing requirements
    Choosing a technology file (.TCH)
    Choosing a strategy file (.SF)
IMPORTING THE DESIGN INTO LAYOUT
SETTING UP THE BOARD
    Making a board outline
    Adding mounting holes
    Adding dimension measurements
    Placing parts
    Finding parts
    Placing parts in the queue
    Inter-tool communication
    Setting up the layers
    Converting a Routing layer to a PLANE Layer
    Adding additional PLANE Layers
    Assigning Nets to layers
    Specifying vias for fanouts
PRE-ROUTING THE BOARD
    Fanning out power and ground
    Fanning out power and ground
    Changing colors of nets
    Manually routing fanouts
    Moving and unrouting fanouts
    Using free vias
    Locking traces
    Viewing DRC errors
    Changing padstack properties
AUTOROUTING THE BOARD
    Controlling the route box
    Loading and editing a routing strategy file
    Running the Autorouter
FINALIZING THE DESIGN
    Post-routing inspection
    Checking routing statistics
    Synchronizing the design with Capture (Back Annotation)
EXAMPLE 2: MIXED ANALOG/DIGITAL DESIGN USING SPLIT POWER, GROUND PLANES
    Mixed signal circuit design in Capture.
    Power and Ground connections to Digital and Analog parts
    Connecting separate Analog and Digital grounds to a split plane
    Using Busses for digital nets
    Defining the layer stack-up for split planes
    Establishing a primary power plane
    Creating split ground planes
    Creating nested power planes with copper pours
    Using anti-copper on plane layers
    Setting up and running the Autorouter
    Moving a routed trace to a different layer
    Adding ground planes and guard traces to routing layers
    Defining vias for flood planes/pours
    Setting the copper pour spacing
    Stitching a ground plane manually
    Using anit-copper obstacles on copper pours
    Routing guard traces and rings
EXAMPLE 3: MULTI-PAGE, MULTI POWER AND GROUND, MIXED A/D DESIGN
    Project setup for PSpice simulation and Layout
    Adding schematic pages to the design
    Using off-page connectors with wires
    Using off-page connectors with busses
    Setting up multiple ground systems
    Settin up PSpice sources
    Performing PSpice simulations
    Preparing the simulated project for Layout
    Assigning a new technology file
    Placing parts on the bottom (back) of a board
    Layer stack-up for a multi-ground system
    Net-layer assignments
    Through-hole and blind Via setup
    Fanning out a board with multiple vias
    Overriding known errors in Layout
    Autorouting with the DRC/Route Box
    Using forced thermals to connect ground planes
    Using the AutoECO to update a board from Capture
EXAMPLE 4: HIGH-SPEED DIGITAL DESIGN
    Layer setup for microstrip transmission lines
    Via design for heat spreaders
    Constructing a heat spreader with copper area obstacles
    Using free vias as heat pipes
    Determining critical trace length of transmission lines
    Routing controlled impedance traces
    Moated ground areas for clock circuits
    Routing curved traces
    Gate and pin swapping
    Stitching a ground plane with the free via matrix
MISCELLANEOUS ITEMS
    Fixing Bad Pad exits
    Design cache—Cleanup, Replace, Update
    Adding test points
    Types of AutoECOs
    Making a custom Capture template
    Making a custom Layout technology/template file
    Using the Stackup Editor
    Submitting Stackup Drawings with Gerber files
    Adding Solder thieves
    Printing a footprint catalog from a PCB design

CHAPTER 10. POST PROCESSING AND BOARD FABRICATION
THE CIRCUIT DESIGN WITH ORCAD
    Schematic design in Capture
    The board design with Layout
    Post processing the design with Layout
FABRICATING THE BOARD
    Choosing a board house
    Setting up a user account
    Submitting Gerber files and requesting a quote
    Annotating the layer types and stackup
    Receipt inspection and testing9
    Non-standard Gerber files9

CHAPTER 11. ADDITIONAL TOOLS
USING PSPICE TO SIMULATE TRANSMISSION LINES
    Simulating digital transmission lines
    Simulating Analog signals
USING MICROSOFT EXCEL WITH A BILL OF MATERIALS GENERATED BY CAPTURE
USING THE SPECCTRA AUTOROUTER WITH LAYOUT
INTRODUCTION TO GERBTOOL
    Opening a Layout generated Gerber file with GerbTool
    Making a .DRL file for a CNC machine
    Panelization
USING CAD TOOLS TO 3-D MODEL A PCB

APPENDICES
    Appendix A: Layout Technology Files
    Appendix B: List of Design Standards
    Appendix C: A Partial List of Packages and Footprints and Some of the Footprints Included in

OrCAD Layout
    Appendix D: Rise and Fall Times for Various Logic Families
    Appendix E: Drill and Screw Dimensions
    Appendix F: References by Subject

BIBLIOGRAPHY AND REFERENCES

INDEX