ARM Architecture Reference Manual (2nd Edition): 1.jpg

Part A: CPU Architecture
Chapter A1 Introduction to the ARM Architecture
A1.1 About the ARM architecture ............................................................................... A1-2
A1.2 ARM instruction set ............................................................................................ A1-5
Chapter A2 Programmer’s Model
A2.1 Data types .......................................................................................................... A2-2
A2.2 Processor modes ............................................................................................... A2-3
A2.3 Registers ............................................................................................................ A2-4
A2.4 General-purpose registers ................................................................................. A2-5
A2.5 Program status registers .................................................................................... A2-9
A2.6 Exceptions ....................................................................................................... A2-13
A2.7 Memory and memory-mapped I/O ................................................................... A2-22
xvi Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E
Chapter A3 The ARM Instruction Set
A3.1 Instruction set encoding ..................................................................................... A3-2
A3.2 The condition field .............................................................................................. A3-5
A3.3 Branch instructions ............................................................................................. A3-7
A3.4 Data-processing instructions .............................................................................. A3-9
A3.5 Multiply instructions .......................................................................................... A3-12
A3.6 Miscellaneous arithmetic instructions ............................................................... A3-14
A3.7 Status register access instructions ................................................................... A3-15
A3.8 Load and store instructions .............................................................................. A3-17
A3.9 Load and Store Multiple instructions ................................................................ A3-21
A3.10 Semaphore instructions ................................................................................... A3-23
A3.11 Exception-generating instructions .................................................................... A3-24
A3.12 Coprocessor instructions .................................................................................. A3-25
A3.13 Extending the instruction set ............................................................................ A3-27
Chapter A4 ARM Instructions
A4.1 Alphabetical list of ARM instructions .................................................................. A4-2
A4.2 ARM instructions and architecture versions ................................................... A4-113
Chapter A5 ARM Addressing Modes
A5.1 Addressing Mode 1 - Data-processing operands ............................................... A5-2
A5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte ........................ A5-18
A5.3 Addressing Mode 3 - Miscellaneous Loads and Stores ................................... A5-34
A5.4 Addressing Mode 4 - Load and Store Multiple ................................................. A5-48
A5.5 Addressing Mode 5 - Load and Store Coprocessor ......................................... A5-56
Chapter A6 The Thumb Instruction Set
A6.1 About the Thumb instruction set ........................................................................ A6-2
A6.2 Instruction set encoding ..................................................................................... A6-4
A6.3 Branch instructions ............................................................................................. A6-6
A6.4 Data-processing instructions .............................................................................. A6-8
A6.5 Load and Store Register instructions ............................................................... A6-15
A6.6 Load and Store Multiple instructions ................................................................ A6-18
A6.7 Exception-generating instructions .................................................................... A6-20
A6.8 Undefined instruction space ............................................................................. A6-21
Chapter A7 Thumb Instructions
A7.1 Alphabetical list of Thumb instructions ............................................................... A7-2
A7.2 Thumb instructions and architecture versions ................................................ A7-104
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. xvii
Chapter A8 The 26-bit Architectures
A8.1 Overview of the 26-bit architectures .................................................................. A8-2
A8.2 Format of register 15 .......................................................................................... A8-4
A8.3 26-bit PSR update instructions .......................................................................... A8-6
A8.4 Address exceptions ............................................................................................ A8-8
A8.5 Backwards compatibility from 32-bit architectures ............................................. A8-9
Chapter A9 ARM Code Sequences
A9.1 Arithmetic instructions ........................................................................................ A9-2
A9.2 Branch instructions ............................................................................................ A9-5
A9.3 Load and Store instructions ............................................................................... A9-7
A9.4 Load and Store Multiple instructions ................................................................ A9-10
A9.5 Semaphore instructions ................................................................................... A9-11
A9.6 Other code examples ....................................................................................... A9-12
Chapter A10 Enhanced DSP Extension
A10.1 About the enhanced DSP instructions ............................................................. A10-2
A10.2 Saturated integer arithmetic ............................................................................. A10-3
A10.3 Saturated Q15 and Q31 arithmetic .................................................................. A10-4
A10.4 The Q flag ........................................................................................................ A10-5
A10.5 Enhanced DSP instructions ............................................................................. A10-6
A10.6 Alphabetical list of enhanced DSP instructions ................................................ A10-8
Part B: Memory and System Architectures
Chapter B1 Introduction to Memory and System Architectures
B1.1 About the memory system ................................................................................. B1-2
B1.2 System-level issues ........................................................................................... B1-4
Chapter B2 The System Control Coprocessor
B2.1 About the System Control coprocessor ............................................................. B2-2
B2.2 Registers ............................................................................................................ B2-3
B2.3 Register 0: ID codes .......................................................................................... B2-6
B2.4 Register 1: Control register .............................................................................. B2-13
B2.5 Registers 2-15 .................................................................................................. B2-17
xviii Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E
Chapter B3 Memory Management Unit
B3.1 About the MMU architecture .............................................................................. B3-2
B3.2 Memory access sequence ................................................................................. B3-4
B3.3 Translation process ............................................................................................ B3-6
B3.4 Access permissions ......................................................................................... B3-16
B3.5 Domains ........................................................................................................... B3-17
B3.6 Aborts ............................................................................................................... B3-18
B3.7 CP15 registers ................................................................................................. B3-23
Chapter B4 Protection Unit
B4.1 About the Protection Unit ................................................................................... B4-2
B4.2 Overlapping regions ........................................................................................... B4-5
B4.3 CP15 registers ................................................................................................... B4-6
Chapter B5 Caches and Write Buffers
B5.1 About caches and write buffers .......................................................................... B5-2
B5.2 Cache organization ............................................................................................ B5-3
B5.3 Types of cache ................................................................................................... B5-5
B5.4 Cachability and bufferability ............................................................................... B5-8
B5.5 Memory coherency ........................................................................................... B5-10
B5.6 CP15 registers ................................................................................................. B5-14
Chapter B6 Fast Context Switch Extension
B6.1 About the FCSE ................................................................................................. B6-2
B6.2 Modified virtual addresses ................................................................................. B6-3
B6.3 Enabling the FCSE ............................................................................................. B6-5
B6.4 CP15 registers ................................................................................................... B6-6
Part C: Vector Floating-point Architecture
Chapter C1 Introduction to the Vector Floating-point Architecture
C1.1 About the Vector Floating-point architecture ......................................................C1-2
C1.2 Overview of the VFP architecture ......................................................................C1-3
C1.3 Compliance with the IEEE 754 standard ............................................................C1-7
C1.4 IEEE 754 implementation choices .....................................................................C1-8
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. xix
Chapter C2 VFP Programmer’s Model
C2.1 Floating-point formats ........................................................................................ C2-2
C2.2 Rounding ............................................................................................................ C2-9
C2.3 Floating-point exceptions ................................................................................. C2-10
C2.4 Flush-to-zero mode .......................................................................................... C2-13
C2.5 Floating-point general-purpose registers ......................................................... C2-14
C2.6 System registers .............................................................................................. C2-19
C2.7 Reset behavior and initialization ...................................................................... C2-26
Chapter C3 VFP Instruction Set Overview
C3.1 Data-processing instructions .............................................................................. C3-2
C3.2 Load and Store instructions ............................................................................. C3-13
C3.3 Register transfer instructions ........................................................................... C3-17
Chapter C4 VFP Instructions
C4.1 Alphabetical list of VFP instructions ................................................................... C4-2
Chapter C5 VFP Addressing Modes
C5.1 Addressing Mode 1 - Single-precision vectors (non-monadic) .......................... C5-2
C5.2 Addressing Mode 2 - Double-precision vectors (non-monadic) ......................... C5-8
C5.3 Addressing Mode 3 - Single-precision vectors (monadic) ................................ C5-14
C5.4 Addressing Mode 4 - Double-precision vectors (monadic) .............................. C5-19
C5.5 Addressing Mode 5 - VFP load/store multiple .................................................. C5-24
Glossary
Index

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