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Contents
Authors
Acknowledgements
Foreword
CHAPTER 1 Introduction
l.l Verification Overview and Challenges
1.1.1 Challenges
1.2 Topics Covered in the book
1.2.1 Introduction
1.2.2 Verification Process
1.2.3 Using SCV for Verification
1.2.4 Test Plan
1.2.5 Test Bench Concepts using SystemC
1.2.6 Methodology
1.2.7 Regression
1.2.8 Functional Coverage
1.2.9 Dynamic Memory Modeling
1.2.10 Post Synthesis/Gate Level Simulation
1.3 Reference Design
1.3.1 Networking Traffic Management and SAR chip
1.3.2 Multimedia Reference Design
CHAPTER 2 Verification Process
2.1 Introduction
2.2 Lint
2.3 High Level verification languages
2.4 Documentation
2.4.1 Documenting verification infrastructure
2.5 Scripting
2.6 Revision control
2.7 Build Process
2.8 Simulation and waveform analysis
2.8.1 Waveform Analysis tool features
2.9 Bug tracking
2.10 Memory modelling
2.11 Regression
2.12 Functional Coverage
2.12.1 Requirements for a Functional Coverage Tools
2.12.2 Limitations of Functional Coverage
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2.13 Code Coverage 41
Using SCV for Verification 45
3.1 Features a verification language 45
3.2 Why use C++ for SCV? 47
CHAPTER 3
3.3 What is randomization 48
3.4 Introduction to SCV 49
3.4.1 Basic Purpose of SCV 49
3.4.2 Basic Language Constructs of SCV 50
3.4.3 Examples of an SCV testbench 53
3.5 Creating A Stimulus Generator using SCV 54
3.5.1 Testbench Structure 54
3.5.2 Randomization 56
3.6 Future of SCV 64
CHAPTER 4 Functional Verification Testplan 65
4.1 Different kinds of Tests 66
4.2 When to Start 68
4.3 Verification plan document 70
4.4 Purpose and Overview 70
4.4.1 Intended Use 70
4.4.2 Project References 70
4.4.3 Goals 70
4.4.4 System Level Testbench: 72
4.4.5 DUV 73
4.4.6 Transaction Verification Modules 74
4.4.7 Packet/Cell Generators 75
4.4.8 CPU Command Generators 76
4.4.9 Packet/Cell Checkers 76
4.4.10 System Level Checker 77
4.4.11 Rate Monitors 77
4.4.12 Simulation Infrastructure 78
4.4.13 Verification Infrastructure 80
4.4.14 System Testing 83
4.4.15 Basic Sanity Testing 83
4.4.16 Memory and Register Diagnostics 83
4.4.17 Application types sanity tests 84
4.4.18 Data path Verification 84
4.4.19 Chip Capacity Tests 85
4.4.20 Framer Model 86
4.4.21 Congestion Check 86
4.4.22 Customer Applications 86
4.4.23 Free Buffer List checking 86
vi Advanced Verification Techniques
4.4.24 Overflow FIFOs 86
4.4.25 Backpressure 86
4.4.26 Negative Tests 86
4.4.27 Block Interface Testing 87
4.4.28 Chip feature testing 87
4.4.29 Random Verification 89
4.4.30 Corner Case Verification 90
4.4.31 Protocol Compliance checking 90
4.4.32 Testing not done in simulation 90
4.4.33 Test Execution Strategy 90
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4.5
4.6
Tests Status/Description document
Summary
CHAPTER 5 Testbench Concepts using SystemC
5.1 Introduction
5.1.1
5.1.2
5.1.3
Modeling Methods
5.2 Unified Verification Methodology(UVM).
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Functional Virtual Prototype
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Transactions
Assertions
Considerations in creating an FVP
Creating the FVP
5.3 Testbench Components
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Verification Communication Modes
Using Transactions in testbenches
Characteristics of Transactions
Hierarchical Transactions
Related Transactions in multiple streams
CHAPTER 6 Verification Methodology
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Introduction
Overall Verification approach
What all tools are needed
Transaction based verification environment:
6.4.1 Elements of TBV
Design verification
6.5.1 System Level Verification
6.5.2 Block Level Verification
6.5.3 Block TVMs at system level: Interface TVMs:
Verification infrastructure
Interface TVMs
Contents vii
Transaction Level Modeling
Block level Verification using TLM
6.7.1
6.7.2
PL3 163
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Other interfaces
6.8 Traffic Generation
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
Traffic generator methodology
Overall Flow
Implementation flow
Interface Driver hookup to traffic Generation
To setup test stimulus for generation:
6.9 Writing Stimulus File
6.9.1 Example stimulus file front end
6.10
6.11
Monitors
Checkers
6.11.1 Methodology used in reference design
6.12 Message Responder
6.12.1
6.12.2
6.12.3
Flow
Basic Structure
Example code
6.13
6.14
6.15
Memory models
Top Level simulation environment
Results of using well defined methodology
CHAPTER 7 Regression/Setup and Run
7.1
7.2
7.3
Goals of Regression
Regression Flow and Phases
7.2.1 Regression Phases
Regression Components
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Bug tracking
Hardware
Host Resources
Load Sharing Software
Regression Scripts
Regression Test Generation
Version control
7.4 Regression features
7.4.1
7.4.2
Important features for regression
Common switches for Regression
7.5 Reporting Mechanism
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
Pass/fail count Report
Summary for each test case
Verbose Report for Debugging if error occurs
Error diagnosis
Exit criteria
viii Advanced Verification Techniques
7.5.6 Verification Metrics 228
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7.6
7.7
Common Dilemmas in Regression
Example of Regression run
7.7.1 Run options.
7.8 Summary
CHAPTER 8 Functional Coverage
8.1 Use of Functional Coverage.
8.1.1
8.1.2
Basic Definition Functional Coverage.
Why Use a Functional Coverage?
8.2 Using Functional Coverage in Verification environment.
8.2.1 Functional and Code Coverage Difference.
8.3 Implementation and Examples of Functional Coverage.
8.3.1
8.3.2
8.3.3
8.3.4
Coverage Model Design.
Transaction Functional Coverage techniques.
Functional Coverage Examples
Role of Functional and Code coverage
8.4 Functional Coverage Tools.
8.4.1
8.4.2
8.4.3
Commercial Functional Coverage Tools.
Features of a good functional coverage tool.
Requirements for a Functional Coverage Tools
8.5 Limitations of Functional Coverage
CHAPTER 9 Dynamic Memory Modeling
9.1
9.2
9.3
9.4
9.5
9.6
Various solutions for simulation memory models
Running simulation with memory models
9.2.1 Built in memory models
Buying commercially available solutions
Comparing Built in and Commercial memory models
Dynamic Memory modeling Techniques
9.5.1
9.5.2
Verilog
Using Wrapper
Example From Reference Design:
9.6.1 Performance comparison
CHAPTER 10 Post Synthesis Gate Simulation
10.1 Introduction
10.1.1 Need for Gate Level Simulation
10.2 Different models for running gate netlist simulation
10.2.1
10.2.2
Gate Simulation with Unit Delay timing
Gate-level simulation with full timing
10.3 Different types of Simulation
10.3.1 Stages for simulation in design flow
10.4 Getting ready for gate simulation
Contents ix
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
Stimulus generation 281
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Back annotating SDF files
Multicycle path
Using Sync Flops
ncpulse and transport delays
Pulse handling by simulator
10.5
10.6
Setting up the gate level simulation
ATE vector Generation
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
Requirement for Functional testing on ATE
Various ATE Stages
Choosing functional simulations for ATE
Generating vectors
Applying vectors back to netlist
Testing at ATE
Problem at speed vectors
10.7
10.8
Setting up simulation for ATE vector generation
Examples of issues uncovered by gate simulations
APPENDIX
0.1
0.2
Common Infrastructure
Simple example based on above methodology
0.2.1
0.2.2
0.2.3
0.2.4
0.2.5
0.2.6
0.2.7
0.2.8
Generator
Sideband
Driver
Monitor
Checker
Stim
SimpleRasTest.h
SimpleRasTest.cc
0.3 Example for standard interfaces:
0.3.1
0.3.2
0.3.3
0.3.4
Code Example for PL3Tx Standard interface:
Code Example for Standard PL3Rx interface
SPI4 interface
Code Example for SPI4 interface
References

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