A_Baseband_Mixed-Signal_Receiver_Front-End_for_1Gbps_Wireless··: A_Baseband_Mixed-Signal_Receiver_Front-End_for_1Gbps_Wireless_Communications_at_60GHz.pdf

A Baseband Mixed-Signal Receiver Front-End for
1Gbps Wireless Communications at 60GHz
David Amory Sobel
Electrical Engineering and Computer Sciences
University of California at Berkeley
Technical Report No. UCB/EECS-2008-45
http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-45.html
May 2, 2008

Table of Contents ...................................................................................................... ii
Acknowledgements ................................................................................................... v
1 Introduction ...................................................................................................... 1
1.1 Trends in High Data-Rate Wireless Systems ............................................ 1
1.2 Recent Developments in 60GHz Regulatory and Industrial Landscape ... 3
1.3 Research Goals and Contributions ............................................................ 4
1.4 Organization of the Dissertation ............................................................... 5
2 The 60GHz Communications Channel ............................................................. 7
2.1 Review of Directional Antenna Technology ............................................. 7
2.1.1 Definition of Terminology..................................................................... 8
2.1.2 Types of Directional Antennae ............................................................ 11
2.1.3 Performance of a Directional Antenna ................................................ 17
2.2 Key Characteristics of the 60GHz Channel ............................................ 21
2.2.1 Reduced Performance of CMOS mm-wave Components ................... 22
2.2.2 Oxygen Absorption and Material Penetration ..................................... 23
2.2.3 Path Loss and Antenna Directionality ................................................. 26
2.2.4 Feasibility of a High Directionality Antenna ...................................... 31
2.2.5 Regulatory Issues and Spectral Efficiency .......................................... 32
2.3 Literature Review of 60GHz Channel Studies ........................................ 34
2.3.1 Material Properties .............................................................................. 35
2.3.2 Channel Properties ............................................................................... 36
2.3.3 Summary of Literature Review ........................................................... 42
2.4 Conclusions ............................................................................................. 44
3 System Design Considerations ....................................................................... 46
3.1 RF Circuit Limitations ............................................................................ 47
3.1.1 Power Amplifier Linearity ................................................................... 47
3.1.2 Local Oscillator Phase Noise ............................................................... 52
3.2 Modulation Schemes ............................................................................... 54
TABLE OF CONTENTS iii
3.2.1 QPSK ................................................................................................... 54
3.2.2 Quadrature Amplitude Modulation ..................................................... 56
3.2.3 OFDM .................................................................................................. 58
3.2.4 Minimum-Shift Keying ....................................................................... 61
3.2.5 Comparison .......................................................................................... 64
3.3 Baseband Architecture Considerations ................................................... 65
3.3.1 Performance Requirements of MSK Baseband Receiver .................... 66
3.3.2 Baseband Architecture Selection ......................................................... 71
3.4 Synchronization Algorithms for Mixed-signal Receivers ....................... 83
3.4.1 Feedback Synchronization Algorithms for Mixed-signal Systems ..... 84
3.4.2 Carrier Phase Estimation ..................................................................... 91
3.4.3 Symbol Timing Estimation .................................................................. 97
3.4.4 Channel Estimation............................................................................ 100
3.5 System Simulations ............................................................................... 105
3.6 Conclusions ........................................................................................... 112
4 Circuit Implementation ................................................................................. 113
4.1 Block-level Architecture ....................................................................... 114
4.2 Carrier Phase Rotator ............................................................................ 115
4.2.1 Gilbert Quad VGA............................................................................. 116
4.2.2 Feedback Tuning Circuit ................................................................... 122
4.2.3 DDFS Current-mode DAC ................................................................ 125
4.3 Decision-feedback Equalizer................................................................. 128
4.3.1 DFE Tap Structure with Programmable Current Bias ....................... 129
4.3.2 Programmable Current Source Load ................................................. 131
4.3.3 Programmable Delay Line ................................................................. 132
4.4 Summing Current Buffer ....................................................................... 133
4.5 Transimpedance Track-and-hold Amplifier .......................................... 136
4.5.1 THTIA amplifier ................................................................................ 138
4.6 Flash ADC ............................................................................................. 140
4.6.1 ADC Architecture and Mismatch Analysis ....................................... 141
4.6.2 Preamplifier ....................................................................................... 150
4.6.3 Averager ............................................................................................ 151
TABLE OF CONTENTS iv
4.6.4 NMOS Comparator............................................................................ 152
4.6.5 CMOS Comparator ............................................................................ 153
4.6.6 Digital Logic ...................................................................................... 154
5 Measurement Results .................................................................................... 155
5.1 ADC Performance ................................................................................. 156
5.2 Carrier Phase Rotator Performance ....................................................... 161
5.3 Decision-Feedback Equalizer Performance .......................................... 164
5.4 Conclusions ........................................................................................... 172
6 Conclusion and Future Work ........................................................................ 173
Bibliography .......................................................................................................... 175

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