A Practical Guide to Low-Power Design: A Practical Guide to Low-Power Design.pdf

Table of Contents
A Practical Guide to Low-Power Design
Foreword . Sect.1 – 2
Preface Sect.1 – 3
Acknowledgements . Sect.1 – 4
References and Bibliography . Sect.1 - 6
Low-Power Links Sect.1 - 9
Power Forward Initiative . Sect.1 - 10
Cadence Low-Power Links . Sect.1 - 10
CPF Terminology Glossary Sect.1 - 12
Design Objects . Sect.1 - 12
CPF Objects Sect.1 - 12
Special Library Cells for Power Management Sect.1 - 14
Introduction to Low Power Sect.1 - 16
Low Power Today . Sect.1 - 16
Power Management . Sect.1 - 18
Complete Low-Power RTL-to-GDSII Flow Using CPF . Sect.1 - 31
A Holistic Approach to Low-Power Intent . Sect.1 - 37
Verification of Low-Power Intent with CPF Sect.1 - 40
Power Intent Validation . Sect.1 - 40
Low-Power Verification . Sect.1 - 42
CPF Verification Summary . . Sect.1 - 57
Front-End Design with CPF Sect.1 - 60
Architectural Exploration Sect.1 - 60
Synthesis Low-Power Optimization . Sect.1 - 62
Automated Power Reduction in Synthesis . Sect.1 - 64
CPF-Powered Reduction in Synthesis . Sect.1 - 69
Simulation for Power Estimation . Sect.1 - 79
CPF Synthesis Summary Sect.1 - 82
Power-Aware Design for Test (DFT) . Sect.1 - 84
Power Domain-Aware DFT . Sect.1 - 84
Power-Aware Test . Sect.1 - 85
CPF Test Summary . Sect.1 - 88
3
Low-Power Implementation with CPF Sect.1 - 90
Introduction to Low-Power Implementation . Sect.1 - 90
Gate-Level Optimization in Power-Aware Physical Synthesis Sect.1 - 93
Clock Gating in Power-Aware Physical Synthesis . Sect.1 - 93
Multi-Vth Optimization in Power-Aware Physical Synthesis Sect.1 - 94
Multiple Supply Voltage (MSV) in Power-Aware Physical Synthesis Sect.1 - 95
Power Shut-Off (PSO) in Power-Aware Physical Synthesis . Sect.1 - 97
Dynamic Voltage/Frequency Scaling (DVFS) Implementation . Sect.1 - 104
Substrate Biasing Implementation . Sect.1 - 105
Diffusion Biasing . Sect.1 - 108
CPF Implementation Summary Sect.1 - 109
ARC Energy PRO: Technology for Active Power Management Sect.2 - 2
Overview of ARC Energy PRO . Sect.2 - 2
The Power Struggle Sect.2 - 2
Designing Low-Power Solutions Sect.2 - 2
Project Subsystem: ARC CPU with Co-Processor Sect.2 - 5
Conclusion . Sect.2 - 8
NEC Electronics: Integrating Power Awareness in SoC Design with CPF . Sect.3 - 2
NEC Electronics and CPF . Sect.3 - 3
Why Low Power? . Sect.3 - 4
Comprehensive Approach to Low Power . Sect.3 - 6
Example of Mobile Phone System SoC . Sect.3 - 7
NEC Electronics CPF Proof-Point Project: NEC-PPP . Sect.3 - 11
Summary . Sect.3 - 18
Fujitsu: CPF in the Low-Power Design Reference Flow . Sect.4 - 2
Fujitsu and CPF . Sect.4 - 4
Low-Power Design Techniques Used by Fujitsu . Sect.4 - 5
Low-Power Test Chip Developed with CPF . Sect.4 - 6
Low-Power Design Flow with CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sect.4 - 7
Review of Low-Power Test Chip Design . Sect.4 - 8
Fujitsu Reference Design Flow 3.0: Low Power with CPF . Sect.4 - 9
Fujitsu’s CPF Low-Power RDF Methodology . Sect.4 -14
Summary . Sect.4 -14
NXP User Experience: Complex SoC Implementation with CPF . Sect.5- 2
Low Power is Critical to NXP . Sect.5- 4
CPF in Action on a Complex SoC Platform Sect.5- 7
Power Network Intent Sect.5- 8
Hierarchical Support for IP and Design Reuse . . . . . . . . . . . . . . . . . . . .Sect.5- 12
4
Scalable Implementation . Sect.5- 13
DFT Impact . Sect.5- 17
CPF-Based Results . Sect.5- 18
Freescale: Wireless Low-Power Design and Verification with CPF . Sect.6- 2
Business Implications of Power . Sect.6- 2
Wireless Carriers and Power . Sect.6- 3
Phone Power and Energy . Sect.6- 3
Active Power Challenge and Design Techniques . Sect.6- 10
Low-Power Design Methodology and CPF . Sect.6- 11
Mobile Application Power Reduction Results . Sect.6- 14
Summary . Sect.6- 15
TSMC: Advanced Design for Low Power at 65nm and Below . Sect.7- 2
TSMC 65nm Low-Power Process . Sect.7- 3
Low-Power Design Techniques . Sect.7- 3
CPF: The Low-Power Standard . Sect.7- 3
The TSMC Proof-Point Project . Sect.7- 5
CPF-Based TSMC Reference Flow 9.0. Sect.7-9
TSMC Low-Power Library: CPF Compliant . Sect.7- 20
Summary . Sect.7- 21
ARM: 1176 IEM Reference Methodology . Sect.8- 2
Introduction . Sect.8- 2
ARM-Cadence Implementation Reference Methodologies . Sect.8- 3
ARM1176 Processor Sect.8- 4
ARM1176JZF-S Low-Power Reference Methodology . Sect.8- 8
Conclusion . Sect.8- 26
Faraday: CPF-Based Low-Power Design Methodology for
Platform-Based SoCs Sect.9- 2
Faraday Design Services and Low-Power Design . Sect.9- 2
Introduction . Sect.9- 3
Faraday CPF Flow . Sect.9- 4
Faraday So Compiler CPF-Enabled Platform-Based
Design for Low-Power . Sect.9- 6
A Low-Power Platform-Based Design Example . Sect.9- 17
Faraday CPF Low-Power
SoCompiler Design Methodology Summary Sect.9- 23
Sequence Design: Early Power Analysis with CPF . Sect.10- 2
Design for Power . Sect.10- 2
Nano CPU Design Overview . Sect.10- 7
Conclusions . Sect.10- 11
5
ARM Cortex iRM: CPF-Driven Low-Power Functionality in
a High-Performance Design Flow Sect.11- 2
ARM and Cadence Collaboration . Sect.11- 2
iRM Flow Setups: Adding Low-Power Functionality to
a High-Performance Design Flow Sect.11- 5
Other Low-Power Functionality Additions to a
High-Performance Design Flow . Sect.11- 16
Conclusions and Availability of ARM/Cadence iRMs . Sect.11- 19
When Do You Know You Have Saved Enough Power? . Sect.12- 2
Impact of Low-Power Design . Sect.12- 2
Power Dissipation . Sect.12- 3
Static Power Optimization . Sect.12- 3
Static Power Optimization . Sect.12- 5
Dynamic Power Optimization . Sect.12- 7
ARM Intelligent Energy Manager™ (IEM) . Sect.12- 11
Power Savings in Multicore Processors . Sect.12- 14
Conclusions . Sect.12- 16
AMD: Power Gating in a High-Performance GPU . Sect.13- 2
AMD and Low Power Sect.13- 2
Front-End Low-Power Logical Design/Verification Flow
and Methodology Sect.13- 9
Back-End Low-Power Physical Design/Verification Flow
and Methodology Sect.13- 14
CPF and Results . Sect.13- 19
Summary of Results Sect.13- 22
ARM 1176-JZFS CPU-Based Low-Power Subsystem:
Methodology to Reduce Electrical and Functional Failure in a
Low-Power Design Sect.14- 2
Abstract . Sect.14- 2
Overview of Ulterior Project Sect.14- 2
Ulterior Implementation . Sect.14- 11
Assembly and Packaging Sect.14- 22
Ulterior Implementation Results . Sect.14- 23
Sonics: CPF Flow for Highly-Configurable
On-Chip Network IP . Sect.15- 2
Overview Sect.15- 2
Sonic Power Management Features Sect.15- 4
CPF Generation and Automation Sect.15- 5
6
Sample SoC Design Sect.15- 6
Sonics CPF-based Low-Power Flow . Sect.15- 7
Low-Power Reference Flow and Tools Sect.15- 12
Conclusion . Sect.15- 14
Virage Logic: Minimizing Design Complexity with
Power-Optimized Physical IP Sect.15- 2
Virage Logic’s IP Portfolio . Sect.16- 2
Economics of Battery Life . Sect.16- 2
Economics of IC Cooling Sect.16- 3
Low Power Design Solutions . Sect.16- 4
Virage Logic Power-Optimization Kit:
Standard Cell Set Sect.16- 5
Standard Cell in the Power Optimization Kit Sect.16- 5
Using Library CPF for Level Shifters, Retention Flops
and Power Switches . Sect.16- 10
40nm SiWare™ Memory Performance/Power
Tradeoffs for Bank and Column Mux Sect.16- 12
Summary Sect.16- 19

Foreword
Energy consumption is a major, if not the major, concern today. The world is facing phenomenal
growth of demand for energy from the Far East coupled with the unabated and substantial appetite for
energy in the U.S. and Europe. At the same time, population growth, economic expansion and urban
development will create greater demand for more personal-mobility items, appliances, devices and
services. Recognizing these worrisome trends, the U.S. Department of Energy (DOE) has identified
the reduction of energy consumption in commercial and residential buildings as a strategic goal. The
Energy Information Administration at DOE attributed 33% of the primary energy consumption
in the U.S. to building space heating and cooling—an amount equivalent to 2.1 billion barrels of
oil. At these levels, even a modest aggregate increase in heating ventilation and air conditioning
(HVAC) efficiency of 1% will provide direct economic benefits to people, enabling reduction and better
management of electric utility grid demand, and reducing dependence on fossil fuels. In addition to
the global relevance of efficient energy usage, there are the micro-economic and convenience concerns
of families, where energy consumption is putting pressure on domestic budgets and where battery life
of home mobile appliances is becoming a major selection factor for consumers.
What can electronics makers do to help? Energy usage can be optimized at the chip, board, box, system,
and network level. At each of these levels there are major gains that can be achieved. Low-power
design has been a substantial research theme for years in IC design. Several important results have
been used to limit energy consumption by fast components such as microprocessors and digital signal
processors. However, while the trend has been improving, the energy consumption of, for example,
Intel and AMD microprocessors is still very important, so that additional research is warranted. As
we traverse layers of abstractions towards systems and networks, the attention paid to low energy
consumption is not increasing proportionally; an important issue to consider moving forward on the
energy conservation path.
Companies should take a holistic view in the energy debate. By carefully managing the interactions
between the different layers of abstraction and by performing a global tradeoff analysis, companies
may take a leadership position. We understand that at this time, enough attention has not been paid
to energy consumption as the design goals have been centered on performance and cost. We also
believe that no one company or institution acting alone can tackle all the issues involved. Leveraging
the supply chain, EDA companies, partners’ research organizations and universities offers a way to
corral the available resources and focus on the problem.
Focusing on the IC design area, process engineers cannot solve the problem alone: 90nm and smaller
process nodes are burning more power with increased design complexity and clock frequencies. Static
power is becoming the predominant source of energy waste. It is up to the design, EDA and IP
community to create methodologies that support better designs, higher performance, lower costs, and
higher engineering productivity—in the context of low-power.
I applaud the efforts of Cadence and the Power Forward Initiative members to develop, in a very a short
period of time, a methodology that uses the Common Power Format (CPF). Partners and competitors
alike worked closely across the entire design and manufacturing ecosystem, from advanced designers
of low-power SoCs, to EDA vendors, to foundries, to IP vendors, to ASIC vendors, to design service
companies. They all recognized the serious needs and formulated a working solution.
I believe that this guide will be a fundamental reference for designers and will help the world in
saving a substantial amount of energy!
Dr. Alberto Sangiovanni-Vincentelli, Professor, The Edgar L. and Harold H. Buttner Chair
of Electrical Engineering, University of California, Berkeley, Co-Founder, CTA and Member
of the Board, Cadence Design Systems.
Sec1:3
Preface
In 2005, it was clear that power had become the most critical issue facing designers of electronic
products. Advanced process technology was in place, power reduction techniques were known and
in use, but design automation and its infrastructure lagged. Low-power design flows were manual,
error-prone, risky, and expensive. The pressure to reduce power was ever more pervasive and the
methodologies available were undesirable.
Recognizing this burgeoning design automation and infrastructure problem, Cadence as the EDA
leader took the initiative to tackle this crisis. To solve the broader design problem holistically, the effort
had to involve the entire electronic product development design chain, including systems and EDA
companies, IP suppliers, foundries, ASIC and design services companies as well as test companies. In
May of 2006, we teamed up with 9 other industry leaders to form the Power Forward Initiative (PFI)
to address the obstacles to lower-power IC design. Within Cadence, technologists from more than
15 business groups realized that incorporating an efficient, automated low-power design solution
into existing design flows would require significant innovation in every step of the design flow.
Through intensive collaboration across the team, it was concluded that implementing advanced
power reduction techniques could be best facilitated by a separate, comprehensive definition of power
intent that could be applied at each step in the design, verification and implementation stages. The
Common Power Format (CPF) was born.
The founding members of PFI: Applied Materials, AMD, ARM, ATI, Freescale, Fujitsu, NEC
Electronics, NXP, and TSMC came together with Cadence to devise, refine and validate the holistic,
CPF-enabled design, verification, and implementation methodology. From the very outset, the goal
was to quickly enable the rapid deployment of a design automation solution that comprehends power
at every stage of the design process. The scope of the R&D effort was huge, spanning software
and algorithmic technology innovation, solution kits, methodology development, and challenging
software validation problems. The vision was simple but success depended on execution at a scope
never attempted before in the history of EDA.
Starting in 2006, the founding companies of PFI created and reviewed the CPF specification. They
then initiated proof-point projects that validated design flows using the Cadence® Low-Power Solution
with complex designs and power intent specified in CPF. By the fall of 2006, PFI members completed
validation of a robust methodology and CPF specification and it was ready for broad deployment and
standardization. The CPF specification was publicly contributed to the Si2 Low-Power Coalition
(LPC) in December 2006. In March 2007, it became a Si2 standard, open and freely available to
everyone in the industry. Since then, the Si2 LPC has continued to investigate new opportunities
for CPF and plot out the evolution of this holistic low-power format. With a growing movement
towards developing greener electronic products, interest in PFI, the Si2 LPC, and the adoption of
CPF-enabled methodology continues to expand rapidly. A uniform vision and belief in the energy
efficient electronic products drove the industry-wide team at an accelerated pace.
The result, A Practical Guide to Low-Power Design, embodies the collective intellectual work and
experience of some of the best engineers in the electronics industry. Our goal in developing this
living, web-based book is to share our experience with the world’s design community. As new designs
are completed, new chapters in low-power design will be written and added to the guide.
Finally, I want to acknowledge all the people involved in this effort. This diverse pan-industry team
of dedicated individuals worked with passion and commitment to bring this solution to life. Working
on a noble cause that has positive and measurable impact on the state of the art in electronic design as
well as positive ramifications for the environment has been exciting for us all. Together, we have built
an ecosystem to accelerate low-power design.
Dr. Chi-Ping Hsu, Corporate Vice President, IC Digital and Power Forward, Cadence Design
Systems.

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