【JSSC200906】火热出炉: 1.pdf

1. A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS
2. An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers
3. A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair
4. A 100 MS/s 4 MHz Bandwidth 70 dB SNR Delta-Sigma ADC in 90 nm CMOS

5. A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees


Abstract—This paper presents a 35-GS/s, 4-bit flash ADC-DAC
with active data and clock distribution trees. At mm-wave clock
frequencies, skew due to mismatch in the clock and data distribution
paths is a significant challenge for both flash and time-interleaved
converter architectures. Afull-rate front-end track and hold
amplifier (THA) may be used to reduce the effect of skew. However,
it is found that the THA output must then be distributed to
the comparators with a bandwidth greater than the sampling frequency
in order to preserve the flat regions of the track and hold
waveform. Instead, if the data and clock distribution have very low
skew, the THA can be omitted thus obviating the associated nonlinearities
and resulting in improved performance. In this work, a
tree of fully symmetric and linear BiCMOS buffers, called a “data
tree”, distributes the input to the comparator bank with a measured
3-dB bandwidth of 16 GHz. The data tree is integrated into
a complete 4-bit ADC including a full-rate input THA that can be
disabled and a 4-bit thermometer-code DAC for testing purposes.
The chip occupies 2.5 mm 3.2 mm including pads and is implemented
in 0.18 m SiGe BiCMOS technology. The ADC consumes
4.5 W from a 3.3 V supply while the DAC operates from a 5 V
supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB
effective resolution bandwidth of 8 GHz and a full-scale differential
input range of 0.24 . With the THA enabled, the performance
degrades rapidly beyond 8 GHz to less than 1-bit, but with
the THA disabled, the ENOB remains better than 3-bits for inputs
up to 11 GHz with an SFDR of better than 26 dB.
Index Terms—Active clock distribution, active data distribution,
analog to digital converter (ADC), BiCMOS amplifiers, digital
to analog converter (DAC), DSP-based equalizers, flash data
converters, mm-wave data converters, SiGe BiCMOS HBT, track
and hold amplifier (THA), transimpedance amplifier (TIA).


6. A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver

Abstract—This paper reports on the realization and the characterization
of an application-specific integrated circuit (ASIC)
intended for the processing of impulse radio ultra-wideband
(IR-UWB) baseband signals. The incoming baseband signals
result from the direct down-conversion of IR-UWB radio-frequency
pulses, which are modulated by a binary frequency-shift
keying (BFSK) scheme. The realized mixed-signal integrated
circuit features an analog demodulation based on the quadricorrelation
method, a non-coherent pulse detector using an
integrate-and-dump operation and a bit-level synchronization
digital circuit. An novel acquisition algorithm intended for low
duty-cycled IR-UWB signals enabling a signal-to-noise ratio (SNR)
estimate is proposed. The baseband ASIC is able to demodulate,
acquire and decode BFSK IR-UWB signals. It requires 13 mW of
supply power during the initial acquisition and 6.5mWduring the
signal tracking phase at a pulse repetition rate (PRR) of 5 MHz.
The circuit is fabricated in a 0.18- m CMOS technology.
Index Terms—Acquisition, baseband processor, BER, CORDIC
algorithm, non-coherent demodulation, quadricorrelation, SNR
estimate, synchronization, ultra-wideband (UWB).

10. On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit
Abstract—On-chip resonant supply noise in the mid-frequency
range (i.e., 50–300 MHz) has been identified as the dominant
supply noise component in modern microprocessors. To overcome
the limited efficiency of conventional decoupling capacitors in reducing
the resonant supply noise, this paper proposes a low-power
digital switched decoupling capacitor circuit. By adaptively
switching the connectivity of decaps according to the measured
supply noise, the amount of charge provided by the decaps is
dramatically boosted leading to an increased damping of the
on-chip supply network. Analysis on the charge transfer during
the switching events shows a 6-13X boost of effective decap value.
Simulations verify the enhanced noise decoupling performance
as well as the effective suppression of the first-droop noise. A
0.13 m test chip including an on-chip resonance generation
circuit and on-chip supply noise sensors was built to demonstrate
the proposed switched decap circuit. Measurements confirm an
11X boost in effective decap value and a 9.8 dB suppression in
supply noise using the proposed circuit. Compared with previous
analog techniques, the proposed digital implementation achieves
a 91% reduction in quiescent power consumption with improved
tolerance to process-voltage-temperature (PVT) variation and
tuning capability for obtaining the optimal switching threshold.
Index Terms—Decoupling capacitor, microprocessor, on-chip
regulator, power supply noise, resonance, switched capacitor.

11. Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder
Abstract—A multiple node upset tolerant, 1.6 Gb/s (8158,
7136) and (4088, 3360) low-density parity-check encoder was
implemented in a five-metal, 0.25 m CMOS process. Temporal
separation coupled with single-event radiation tolerant flip-flops
was used to harden the data path. A reduced sensitive cross-section
combinational logic structure was used to harden the custom
multiply accumulate blocks. This circuit structure is composed of
a dual-rail NMOS-only pass-transistor network driving a cross
coupled output buffer. By adding the output buffer section, only
a small region of the buffer itself is vulnerable for propagation
of a single-event transient. Single-event upset immunity with a
linear energy transfer threshold of greater than 33 MeV cm􀀀/mg
and a saturation cross-section of just 0.075 m􀀀/bit was achieved
for the 4 K encoder. A linear energy transfer threshold of greater
than 17 MeV cm􀀀/mg with a saturation cross-section of just
0.3 m􀀀/bit was achieved for the 8 K encoder. This results in a
CREME96 expected mean time between failure of 1700 years for a
geosynchronous orbit. Multiple node upsets as a problem increases
as smaller geometry processes are used for space electronics. A
mathematical basis for this reduced cross-section, multiple upset
combinational logic design method is presented.

12. A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode


Abstract—A voltage scalable 0.26 V, 64 kb 8T SRAM with 512
cells per bitline is implemented in a 130 nm CMOS process. Utilization
of the reverse short channel effect in a SRAM cell design
improves cell write margin and read performance without the aid
of peripheral circuits. A marginal bitline leakage compensation
(MBLC) scheme compensates for the bitline leakage current which
becomes comparable to a read current at subthreshold supply voltages.
The MBLC allows us to lower􀀀􀀀 to 0.26 V and also eliminates
the need for precharged read bitlines. A floating read bitline
and write bitline scheme reduces the leakage power consumption.
A deep sleep mode minimizes the standby leakage power consumption
without compromising the hold mode cell stability. Finally, an
automatic wordline pulse width control circuit tracks PVT variations
and shuts off the bitline leakage current upon completion of
a read operation.


13. An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered
      High-Current Implants

[quote]12. A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode


Abstract—A voltage scalable 0.26 V, 64 kb 8T SRAM with 512
cells per bitline is implemented in a 1 ...
tianxian 发表于 2009-5-30 00:48

                               
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网速实在惊人，剩下的抽空再传
:26bb :26bb
睡觉去了
：23de

坚持一下
12
13

顶

7. Design of Three-Stage Class-AB 16ohm Headphone Driver Capable of Handling Wide Range of Load Capacitance

Abstract—In this paper, the effect of load capacitance variation
on the location of the closed loop poles of three-stage amplifiers
is analyzed and a frequency compensation scheme that automatically
adjusts the damping factor according to the load capacitance
is proposed. A class-AB 16 􀀀 headphone driver designed using
the proposed scheme in 0.13 m technology can handle 1 pF to
22 nF capacitive load while consuming as low as 1.2 mW of quiescent
power. It can deliver a peak power of 40 mW (1.6 Vpp swing)
to the load with 84.8 dB THD and 92 dB peak SNR. It occupies
0.1 mm􀀀 area.
Index Terms—Class-AB amplifiers, class-AB drivers, audio
power amplifiers, headphone drivers, multi-stage amplifiers,
capacitive loaded amplifiers.

8. All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform


Abstract—This paper proposes an all-digital measurement circuit
called a “gated oscillator” to capture the waveforms of dynamic
power supply noise. An improved gated oscillator with a
power-gating structure is also proposed. The gated oscillator is
constructed using standard cells, and thus is easily embedded in
SoCs. Its performance was evaluated using test chips fabricated in
a 90 nm process. The gated oscillator achieved 5.3–5.9 Gsample/s
with an area of 10.08 6.72 m􀀀, and the improved power gating
structure achieved 6.6–8.3 Gsample/s in a 90 nmprocess. The characteristics
of the gated oscillator and related design issues are also
discussed. These characteristics were verified on silicon. We evaluated
the effect of the decoupling capacitance based on measurement
results obtained using the gated oscillator, and demonstrated
that it could be used to verify power integrity.
Index Terms—Decoupling capacitance, measurement circuit,
power supply noise, ring oscillator.


9. Reduction of Inductive Crosstalk Using Quadrupole Inductors
Abstract—Interference due to inductor crosstalk is a growing
concern in modern RFICs where inductors are placed in close
proximity. A quadrupole inductor is explored as a method to
reduce inductive crosstalk. A quadrupole inductor and standard
inductor are compared with respect to inductance, quality factor,
and area. Then, physics-based calculations are corroborated with
simulation and measurement to predict crosstalk reduction as a
function of position. Measurements verify up to a 31 dB reduction
in crosstalk. Finally, phase noise measurements of voltage-controlled
oscillators show that the quadrupole inductor can be used
in circuits without negatively impacting performance.
Index Terms—Crosstalk, inductance measurement, inductors,
voltage-controlled oscillators.

14. A Spectral-Scanning Nuclear Magnetic Resonance Imaging (MRI) Transceiver

Abstract—An integrated spectral-scanning nuclear magnetic
resonance imaging (MRI) transceiver is implemented in a 0.12 m
SiGe BiCMOS process. The MRI transmitter and receiver
circuitry is designed specifically for small-scale surface MRI
diagnostics applications where creating low (below 1 T) and
inhomogeneous magnetic field is more practical. The operation
frequency for magnetic resonance detection and analysis is tunable
from 1 kHz to 37 MHz, corresponding to 0–0.9 T magnetization
for 􀀀H (Hydrogen). The concurrent measurement bandwidth is
approximately one frequency octave. The chip can also be used
for conventional narrowband nuclear magnetic resonance (NMR)
spectroscopy from 1 kHz up to 250 MHz. This integrated transceiver
consists of both the magnetic resonance transmitter which
generates the required excitation pulses for the magnetic dipole
excitation, and the receiver which recovers the responses of the
dipoles.
Index Terms—Nuclear magnetic resonance (NMR) spectroscopy,
magnetic resonance imaging (MRI), coherent detection,
Torrey-Bloch equation, nuclear magnetic dephasing

15. A Bio-Inspired Active Radio-Frequency Silicon Cochlea

Abstract—Fast wideband spectrum analysis is expensive in
power and hardware resources. We show that the spectrum-analysis
architecture used by the biological cochlea is extremely
efficient: analysis time, power and hardware usage all scale
linearly with , the number of output frequency bins, versus
􀀀  for the Fast Fourier Transform. We also demonstrate
two on-chip radio frequency (RF) spectrum analyzers inspired
by the cochlea. They use exponentially-tapered transmission lines
or filter cascades to model cochlear operation: Inductors map to
fluid mass, capacitors to membrane stiffness and active elements
(transistors) to active outer hair cell feedback mechanisms. Our
RF cochlea chips, implemented in a 0.13 m CMOS process, are 3
mm 1.5 mm in size, have 50 exponentially-spaced output channels,
have 70 dB of dynamic range, consume 300 mW of power
and analyze the radio spectrum from 600 MHz to 8 GHz. Our
work, which delivers insight into the efficiency of analog computation
in the ear, may be useful in the front ends of ultra-wideband
radio systems for fast, power-efficient spectral decomposition and
analysis. Our novel rational cochlear transfer functions with zeros
also enable improved audio silicon cochlea designs with sharper
rolloff slopes and lower group delay than prior all-pole versions.
Index Terms—Bio-inspired, cochlear models, radio frequency
(RF), silicon cochlea, spectrum analysis.

16. Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

Abstract—The CMOS image sensor computes two-dimensional
convolution of video frames with a programmable digital kernel
of up to 8 8 pixels in parallel directly on the focal plane. Three
operations, a temporal difference, a multiplication and an accumulation
are performed for each pixel readout. A dual-memory pixel
stores two video frames. Selective pixel output sampling controlled
by binary kernel coefficients implements binary-analog multiplication.
Cross-pixel column-parallel bit-level accumulation and frame
differencing are implemented by switched-capacitor integrators.
Binary-weighted summation and concurrent quantization is performed
by a bank of column-parallel multiplying analog-to-digital
converters (MADCs). Asimple digital adder performs row-wise accumulation
during ADC readout. A 128 128 active pixel array
integrated with a bank of 128 MADCs was fabricated in a 0.35 m
standard CMOS technology. The 4.4 mm 2.9 mm prototype
is experimentally validated in discrete wavelet transform (DWT)
video compression and frame differencing.
Index Terms—Block-matrix image transform, CMOS image
sensor, focal-plane image processing, multiplying algorithmic
ADC.

：cacakiki2de

over

:24bb


jssc  这样顶级论文大家不需要吗？

good journal, why no one download?