Key Issues of RF/ RFIC Circuit Design （英文版）
By 李缉熙（Richard Chi-Hsi） 2005
《KEY ISSUES in RF/RFIC CIRCUIT DESIGN》自出版以来，广受读者关注和好评。为了更好地满足国内相关院校和广大学习者的需求，东南大学王志功教授主持翻译本书的中文版。
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Chapter 1 Importance of Impedance Matching 1
1.1 Difference between RF and Digital Circuit Design 1
1.1.1 Case # 1: Digital Circuits at Low Data Rate 2
1.1.2 Case # 2: Digital Circuits at High Data Rate 5
1.2 Significance of Impedance Matching 7
1.2.1 Power Transportation from a Source to a Load 7
1.2.2 Maximizing of Power Transportation without Phase Shift 8
1.2.3 Conjugate Impedance Matching and Voltage Reflection Coefficient 10
1.2.4 Impedance Matching Network 11
1.3 Problems due to Unmatched Status of Impedance 14
1.3.1 General Expression of Power Transportation 14
1.3.2 Power Instability and Additional Power Loss 17
1.3.3 Additional Distortion and Quasi-Noise 19
1.3.4 Power Measurement 22
1.3.5 Power Transportation and Voltage Transportation 24
1.3.6 Burning of a Transistor 28
References 29
Chapter 2 Impedance Matching 30
2.1 Impedance Measured by Small Signal 30
2.1.1 Impedance Measured by S Parameter Measurement 30
2.1.2 The Smith Chart: Impedance and Admittance Coordination 31
2.1.3 Accuracy of Smith Chart 35
2.1.4 Relationship between the Impedance in Series and in Parallel 36
2.2 Impedance Measured by Large Signal 39
2.3 Impedance Matching 42
2.3.1 One Part Matching Network 42
2.3.2 Recognition of Regions in a Smith Chart 44
2.3.3 Two Parts Matching Network 45
2.3.4 Two Parts Upward and Downward Impedance Transformer 55
2.3.5 Three Parts Matching Network and Impedance Transformer 59
2.3.5.1 Topology Limitation of Two Parts Matching Network 59
2.3.5.2 Π Type Matching Network 61
2.3.5.3 T Type Matching Network 67
2.4 Some Useful Schemes for Impedance Matching 73
2.4.1 Designs and Tests when ZL is not 50 Ω 73
2.4.2 Conversion between “T” and “Π” Type Matching Network 74
2.4.3 Parts in a Matching Network 76
2.4.4 Impedance Matching between Power Transportation Units 77
2.4.5 Impedance Matching for a Mixer 78
References 79
Chapter 3 RF Grounding 81
3.1 A True Story 81
3.2 Three Components for RF Grounding 83
3.2.1 “Zero” Capacitors 83
3.2.2 Micro Strip Line 87
3.2.3 RF Cable 92
3.3 Examples of RF grounding 94
3.3.1 Test PCB 94
3.3.1.1 Small Test PCB 95
3.3.1.1.1 Basic Types of Test PCB 95
3.3.1.1.2 RF Grounding with a Rectangular Metallic Frame 99
3.3.1.1.3 An Example 100
3.3.1.2 Large Test PCB 103
3.3.1.2.1 RF Grounding by “Zero” Chip Capacitors 103
3.3.1.2.2 RF Grounding by a Runner or a Cable
with Half or Quarter Wavelength 105
3.3.2 Isolation between Input and Output in a Mixer or an Up-converter 108
3.3.3 Calibration for Network Analyzer 109
3.4 RF Grounding for Reduction of Return Current Coupling 111
3.4.1 A Circuit Built by Discrete Parts on a PCB 111
3.4.2 RFICs 114
References 118
Chapter 4 Equivalent Circuits of Passive Chip Parts 119
4.1 Modeling of Passive Chip Parts 120
4.2 Characterizing of Passive Chip Parts by Network Analyzer 122
4.3 Extraction from the Measurement by Network Analyzer 124
4.3.1 Chip Capacitor 124
4.3.2 Chip Inductor 129
4.3.3 Chip Resistor 135
4. 4 Summary 138
References 139
Chapter 5 Single-ended Stage and Differential Pair 140
5.1 Basic Single-ended Stage 140
5.1.1 General Description 140
5.1.2 Small Signal Model of a Bipolar Transistor 142
5.1.2.1 Impedance of a CE (Common Emitter) Device 144
5.1.2.2 Impedance of a CB (Common Base) Device 146
5.1.2.3 Impedance of a CC (Common Collector) Device 149
5.1.2.4 Comparison between CE, CB, and CC Device 151
5.1.3 Small Signal Model of a MOSFET 152
5.1.3.1 Impedance of a CS (Common source) Device 155
5.1.3.2 Impedance of a CG (Common gate) Device 156
5.1.3.3 Impedance of a CD (Common drain) Device 157
5.1.3.4 Comparison between CS, CG, and CD Device 158
5.2 Differential pair 160
5.2.1 DC Transfer Characteristic 160
5.2.1.1 DC Transfer Characteristic of a Bipolar Differential Pair 160
5.2.1.2 DC Transfer Characteristic of a CMOS Differential Pair 162
5.2.2 Small Signal Characteristic 163
5.2.3 Improvement of CMRR 171
5.2.4 Increase of Voltage Swing 173
5.2.5 Cancellation of Interference 174
5.2.6 Noise in a Differential Pair 176
5.3 Apparent Difference between Single-ended Stage and
Differential pair 181
5.4 DC Offset 184
5.4.1 DC Offset in a Single-ended Device 184
5.4.2 Zero DC Offset in a Pseudo-Differential Pair 186
5.4.3 Why “Zero” IF or Direct Conversion 188
5.4.4 DC Offset Cancellation 190
5.4.4.1 “Chopping” Mixer 190
5.4.4.2 DC Offset Calibration 196
5.4.4.3 Hardware Schemes 197
References 199
Chapter 6 Balun 201
6.1 Coaxial Cable Balun 201
6.2 Ring Micro Strip Line Balun 203
6.3 Transformer Balun 206
6.4 Transformer Balun Composed by Two
Stacked 2x2 Transformers 209
6.5 LC Balun 213
References 222
Chapter 7 Tolerance Analysis 223
7.1 Importance of Tolerance Analysis 223
7.2 Fundamentals of Tolerance Analysis 225
7.2.1 Tolerance and Normal Distribution 225
7.2.2 6σ, Cp, and Cpk 230
7.2.3 Yield Rate and DPU 234
7.2.4 Poisson Distribution 237
7.3 Approach to 6σ Design and Production 238
7.4 An Example: Tunable Filter Design 243
7.4.1 Description of the Tunable Filter Design 244
7.4.2 Monte-Carlo Analysis 245
7.5 Appendix: Table of the Normal Distribution 251
References 252
Chapter 8 Prospect of RFIC Design 253
8.1 History of RFIC development 253
8.2 Isolation between Blocks in an RFIC 256
8.2.1 Definition and Measurement of Isolation 256
8.2.2 Isolation Technology 257
8.3 Low Q Value of Spiral Inductor 272
8.3.1 Skin Effect 273
8.3.2 Attenuation due to Substrate 274
8.3.3 Flux Leakage 275
8.3.4 Flux Cancellation 277
8.3.5 A Possible Solution --- Negative Resistance Compensation 280
8.3.5.1 Negative Resistance Generator with a FET 282
8.3.5.2 Negative Resistance Generator with Transformer 283
8.4 Layout 284
8.4.1 Runners 284
8.4.2 Parts 290
8.4.3 Variable Parts in RFIC 292
8.4.4 Symmetry 294
8.4.5 Via 295
8.4.6 Free Space on the Die 296
8.5 Two Challenges in an RFIC or SOC Design 297
8.5.1 Isolation 297
8.5.2 High Q Inductor for IC 298
References 299
Chapter 9 Noise, Gain, and Sensitivity of a Receiver 301
9.1 Noise in a Circuit Block or a System 301
9.1.1 Noise Sources 301
9.1.1.1 Shot Noise 301
9.1.1.2 Thermal Noise 302
9.1.1.3 Flicker Noise (1/f Noise) 303
9.1.2 Definition of Noise Figure 304
9.1.3 Noise Figure in a Noisy Two Port Block 305
9.1.4 Minimum Noise Figure and Equivalent Noise Resistor 310
9.1.4.1 Noise in a MOSFET 310
9.1.4.2 Noise in a Bipolar Device 311
9.2 Gain 314
9.2.1 Definition of Power Gains 314
9.2.2 Power Gain and Voltage Gain 318
9.3 Sensitivity 319
9.3.1 Standard Noise Source 319
9.3.2 Equivalent Input Noise 320
9.3.3 Sensitivity of a Receiver 320
References 322
Chapter 10 Non-linearity and Spurious Products 323
10.1 Spurious products 323
10.1.1 Harmonics 323
10.1.2 Complicated Spurious Products 325
10.2 IP (Intercept Point) and IMR (Inter-Modulation Rejection) 328
10.3 3rd order Intercept Point and Spurious Product 331
10.4 1 dB Compression Point and IP3 335
10.5 2nd Order Intercept Point and Spurious Product 337
10.6 Distortion 339
References 340
Chapter 11 Cascaded Equations and System
Analysis 342
11.1 Cascaded Equation for Power Gain 342
11.2 Cascaded Equation for Noise Figure 345
11.3 Cascaded Equation for Intercept Point 348
11.4 Application of Cascaded Equations
in the System Analysis 357
References 359
Chapter 12 From Analog to Digital
Communication system 360
12.1 Modulation in an Analog Communication System 360
12.2 Encoding in a Digital Communication System 365
12.2.1 NRZ (Non-Return to Zero) and Manchester Format 365
12.2.2 BPSK (Binary Phase Shift Keying) 367
12.2.3 QPSK (Quadrature Phase Shift Keying), OQPSK, MSK 369
12.2.4 FSK (Frequency Shift Keying), CPFSK 373
12.3 Decoding and Bit-Error Probability 374
12.4 Error Correction Schemes 377
References 380
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本帖最后由 drjiachen 于 2008-12-30 10:53 编辑 ]
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Key Issues of RF/ RFIC Circuit Design: Key Issues in RF and RFIC Circuit Design.rar
