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LowNoiseOscillatorDesignTechniques

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Low-Noise Local Oscillator Design Techniques
using a DLL-based Frequency Multiplier
for Wireless Applications

Copyright ã 2000
by
George Chien

[ 本帖最后由 lswluo 于 2008-12-12 10:17 编辑 ]

Abstract

Low-Noise Local Oscillator Design Techniques
using a DLL-based Frequency Multiplier
for Wireless Applications
by
George Chien
Doctor of Philosophy in Engineering -
Electrical Engineering and Computer Sciences
University of California, Berkeley
Professor Paul R. Gray, Chair


The fast growing demand of wireless communications for voice and data has
driven recent efforts to dramatically increase the levels of integration in RF transceivers.
One approach to this challenge is to implement all the RF functions in the low-cost CMOS
technology, so that RF and baseband sections can be combined in a single chip. This in
turn dictates an integrated CMOS implementation of the local oscillators with the same or
even better phase noise performance than its discrete counterpart, generally a difficult task
using conventional approaches with the available low-Q integrated inductors. This is a particularly
severe problem in RF systems such as AMPS, where the channel spacing is small
and close-in phase noise must be extremely low.
In this thesis the fundamental performance limit of a local oscillator design using a
DLL-based frequency multiplier is investigated. The distinctive timing jitter accumulation
pattern of a DLL-based frequency multiplier is analyzed in detail to predict the phase
noise performance based on the thermal-noise-induced jitter of the source-coupled differential
CMOS delay cell implementation. The result suggests an unique phase noise signature
compared to a PLL approach using a VCO. Due to the limited timing jitter accumulation in a DLL, the close-in phase noise performance of the DLL-based frequency
multiplier is much lower than that of a monolithic VCO.
The specific research contributions of this work include (1) proposing a new local
oscillator architecture using a DLL-based frequency multiplier that breaks the traditional
LO phase noise limitations, (2) an analytical model that describes the phase noise performance
of the proposed local oscillator architecture, (3) the application of the DLL-based
frequency multiplier to a monolithic CMOS low-phase-noise local oscillator for cellular
telephone applications.
To demonstrate the proposed concept, a fully integrated CMOS local oscillator utilizing
a DLL-based frequency multiplier technique to synthesize a 900MHz carrier with
low close-in phase noise was designed. This prototype, implemented in a standard 0.35mm
CMOS technology, achieves -123dBc/Hz phase noise at 60kHz offset while dissipating
130mW from a 3.3V supply, meeting the requirements of the IS-137 dual-mode standard.

Table of Contents
Chapter 1 Introduction
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Research Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Frequency Synthesizer in Wireless Communication Systems
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Superheterodyne . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Direct Conversion (Zero-IF) . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Low-IF Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.4 Block-Down Conversion: Wideband IF with Double
Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Direct Conversion Transmitter . . . . . . . . . . . . . . . . . . . . 21
2.3.2 Double Conversion Transmitter . . . . . . . . . . . . . . . . . . . 23
2.3.3 PLL-based Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 Non-idealities in Frequency Synthesizer and Their Impacts . . 27
2.4.1 Role of Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . 27
2.4.2 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4.3 Spurious Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 3 Frequency Synthesizer Architectures
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 Phase Locked Loop Fundamentals . . . . . . . . . . . . . . . . . . . . . . 46
3.2.1 PLL Linearized Model . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.2 Performance Limitation . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.3 Current Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 Integrated Voltage Controlled Oscillators . . . . . . . . . . . . . . . . . 54
3.3.1 Monolithic Integrated LC-tank . . . . . . . . . . . . . . . . . . . . 55
3.3.2 Process-Enhanced Inductors . . . . . . . . . . . . . . . . . . . . . 57
3.3.3 Integrated Ring Oscillator VCO . . . . . . . . . . . . . . . . . . . 60
3.3.4 Micromachined-Based VCO . . . . . . . . . . . . . . . . . . . . . . 62
3.3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4 Architecture Alternatives for Frequency Synthesizers . . . . . . . 63
3.4.1 Wide Loop Bandwidth PLL . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.2 New Architecture for Narrow-Channel Wireless System . . 65
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Chapter 4 DLL-based Frequency Multiplier Fundamentals
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 The Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2.2 Timing Jitter Accumulation . . . . . . . . . . . . . . . . . . . . . . 74
4.3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.1 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.2 Spurious Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.4 Performance Implications for Wireless Communications . . . . 89
4.4.1 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.4.2 Spurious Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 5 CMOS Local Oscillator Design using the DLL-based
Frequency Multiplier Technique
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2 Small-Signal AC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.1 Voltage-Controlled Delay Line . . . . . . . . . . . . . . . . . . . . 99
5.2.2 Phase Detector and Charge Pump . . . . . . . . . . . . . . . . 102
5.2.3 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.4 Overall DLL Transfer Function . . . . . . . . . . . . . . . . . . 104
5.2.5 Edge Combiner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3 CMOS Delay Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.1 Basic Delay Chain Design . . . . . . . . . . . . . . . . . . . . . . 110
5.3.2 Interstage Gain Consideration . . . . . . . . . . . . . . . . . . . 111
5.3.3 Voltage Swing Consideration . . . . . . . . . . . . . . . . . . . . 112
5.3.4 Replica Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3.5 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4 Control Circuitry Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.4.1 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.4.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.4.3 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.5 Edge Combiner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 6 Prototype Implementation
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.2 IS-137 Dual-Mode Standard . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.4 Chip Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.5 Master Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.6 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.7 Performance Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.8 1/f Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.9 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.11 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Chapter 7 Experimental Results
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.3 Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.4 Spurious Tone Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Chapter 8 Conclusion
8.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Appendix A RMS Timing Jitter for Differential Delay Cell
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
A.2 RMS Timing Jitter Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 164
A.3 Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
A.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Appendix B Autocorrelation and Power Spectra
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
B.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
B.3 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
B.4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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