Verilog Digital System Design: Verilog Digital System Design.2007.rar

Verilog Digital System Design (Professional Engineering) (Hardcover)by Zainalabedin Navabi (Author)


Hardcover: 453 pages Publisher: McGraw-Hill Professional Publishing; Bk&CD Rom edition (2007) Language: English ISBN-10: 0070471649 ISBN-13: 978-0070471641

Product Description
Verilog hardware description language is used to design high density VLSI, allowing designers to lay millions of transistors on single substrate. This book provides detailed, heavily-exampled instruction for designing with IEEE standard Verilgo.

From the Author
The book comes with a CD that contains Verilog and VHDL simulators, lecture material, and a web based electronic indexing tool that we call Verilog Circuit Navigator. To see how the navigator works, please send email to navabi@ece.neu.edu for a demo version.

Contents

Preface xiii
Chapter 1. Digital System Design Automation with Verilog 1
1.1 Digital Design Flow 2
1.1.1 Design entry 3
1.1.2 Testbench in Verilog 4
1.1.3 Design validation 4
1.1.4 Compilation and synthesis 7
1.1.5 Postsynthesis simulation 10
1.1.6 Timing analysis 10
1.1.7 Hardware generation 10
1.2 Verilog HDL 10
1.2.1 Verilog evolution 11
1.2.2 Verilog attributes 11
1.2.3 The Verilog language 13
1.3 Summary 13
Problems 13
Suggested Reading 14
Chapter 2. Register Transfer Level Design with Verilog 15
2.1 RT Level Design 15
2.1.1 Control/data partitioning 16
2.1.2 Data part 16
2.1.3 Control part 17
2.2 Elements of Verilog 18
2.2.1 Hardware modules 18
2.2.2 Primitive instantiations 19
2.2.3 Assign statements 20
2.2.4 Condition expression 20
2.2.5 Procedural blocks 20
2.2.6 Module instantiations 21
2.3 Component Description in Verilog 22
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2.3.1 Data components 22
2.3.2 Controllers 29
2.4 Testbenches 33
2.4.1 A simple tester 33
2.4.2 Tasks and functions 34
2.5 Summary 34
Problems 35
Suggested Reading 35
Chapter 3. Verilog Language Concepts 37
3.1 Characterizing Hardware Languages 37
3.1.1 Timing 37
3.1.2 Concurrency 39
3.1.3 Timing and concurrency example 40
3.2 Module Basics 41
3.2.1 Code format 41
3.2.2 Logic value system 41
3.2.3 Wires and variables 42
3.2.4 Modules 42
3.2.5 Module ports 43
3.2.6Names 43
3.2.7 Numbers 44
3.2.8 Arrays 46
3.2.9 Verilog operators 48
3.2.10 Verilog data types 54
3.2.11 Array indexing 58
3.3 Verilog Simulation Model 59
3.3.1 Continuous assignments 61
3.3.2 Procedural assignments 65
3.4 Compiler Directives 71
3.4.1 `timescale 71
3.4.2 `default-nettype 71
3.4.3 `include 71
3.4.4 `define 71
3.4.5 `ifdef, `else,`endif 72
3.4.6 `unconnected-drive 72
3.4.7 `celldefine,`endcelldefine 72
3.4.8 `resetall 72
3.5 System Tasks and Functions 72
3.5.1 Display tasks 73
3.5.2 File I/O tasks 73
3.5.3 Timescale tasks 74
3.5.4 Simulation control tasks 74
3.5.5 Timing check tasks 74
3.5.6 PLA modeling tasks 74
3.5.7 Conversion functions for reals 75
3.5.8 Other tasks and functions 75
3.6 Summary 76
Problems 76
Suggested Reading 80
vi Contents
Chapter 4. Combinational Circuit Description 81
4.1 Module Wires 81
4.1.1 Ports 81
4.1.2 Interconnections 82
4.1.3 Wire values and timing 82
4.1.4 A simple testbench 84
4.2 Gate Level Logic 85
4.2.1 Gate primitives 85
4.2.2 User defined primitives 87
4.2.3 Delay formats 88
4.2.4 Module parameters 90
4.3 Hierarchical Structures 93
4.3.1 Simple hierarchies 93
4.3.2 Vector declarations 95
4.3.3 Iterative structures 96
4.3.4 Module path delay 99
4.4 Describing Expressions with Assign Statements 102
4.4.1 Bitwise operators 102
4.4.2 Concatenation operators 104
4.4.3 Vector operations 104
4.4.4 Conditional operation 105
4.4.5 Arithmetic expressions in assignments 108
4.4.6 Functions in expressions 109
4.4.7 Bus structures 110
4.4.8 Net declaration assignment 111
4.5 Behavioral Combinational Descriptions 112
4.5.1 Simple procedural blocks 113
4.5.2 Timing control 113
4.5.3 Intra-assignment delay 116
4.5.4 Blocking and nonblocking assignments 116
4.5.5 Procedural if-else 118
4.5.6 Procedural case statement 120
4.5.7 Procedural for statement 122
4.5.8 Procedural while loop 123
4.5.9 A multilevel description 124
4.6 Combinational Synthesis 125
4.6.1 Gate level synthesis 127
4.6.2 Synthesizing continuous assignments 128
4.6.3 Behavioral synthesis 129
4.6.4 Mixed synthesis 132
4.7 Summary 132
Problems 132
Suggested Reading 134
Chapter 5. Sequential Circuit Description 135
5.1 Sequential Models 135
5.1.1 Feedback model 136
5.1.2 Capacitive model 136
5.1.3 Implicit model 136
Contents vii
5.2 Basic Memory Components 137
5.2.1 Gate level primitives 137
5.2.2 User defined sequential primitives 139
5.2.3 Memory elements using assignments 140
5.2.4 Behavioral memory elements 142
5.2.5 Flip-Flop timing 149
5.2.6 Memory vectors and arrays 151
5.3 Functional Registers 157
5.3.1 Shift registers 157
5.3.2 Counters 161
5.3.3 LFSR and MISR 163
5.3.4 Stacks and queues 167
5.4 State Machine Coding 171
5.4.1 Moore machines 171
5.4.2 Mealy machines 174
5.4.3 Huffman coding style 176
5.4.4 A more modular style 180
5.4.5 A ROM based controller 181
5.5 Sequential Synthesis 181
5.5.1 Latch models 183
5.5.2 Flip-flop models 184
5.5.3 Memory initialization 185
5.5.4 General sequential circuit synthesis 186
5.6 Summary 186
Problems 187
Suggested Reading 189
Chapter 6. Component Test and Verification 191
6.1 Testbench 191
6.1.1 Combinational circuit testing 192
6.1.2 Sequential circuit testing 194
6.2 Testbench Techniques 195
6.2.1 Test data 196
6.2.2 Simulation control 197
6.2.3 Limiting data sets 198
6.2.4 Applying synchronized data 199
6.2.5 Synchronized display of results 200
6.2.6 An interactive testbench 201
6.2.7 Random time intervals 204
6.2.8 Buffered data application 205
6.3 Design Verification 206
6.4 Assertion Verification 207
6.4.1 Assertion verification benefits 208
6.4.2 Open verification library 208
6.4.3 Using assertion monitors 209
6.4.4 Assertion templates 216
6.5 Text Based Testbenches 219
6.6 Summary 220
Problems 220
Suggested Reading 221
viii Contents
Chapter 7. Detailed Modeling 223
7.1 Switch Level Modeling 223
7.1.1 Switch level primitives 224
7.1.2 The basic switch 225
7.1.3 CMOS gates 226
7.1.4 Pass gate logic 230
7.1.5 Switch level memory elements 234
7.2 Strength Modeling 241
7.2.1 Strength values 242
7.2.2 Strength used in resolution 244
7.2.3 Strength reduction 247
7.3 Summary 250
Problems 250
Suggested Reading 251
Chapter 8. RT Level Design and Test 253
8.1 Sequential Multiplier 253
8.1.1 Shift-and-add multiplication process 254
8.1.2 Sequential multiplier design 256
8.1.3 Multiplier testing 261
8.2 von Neumann Computer Model 265
8.2.1 Processor and memory model 265
8.2.2 Processor model specification 266
8.2.3 Designing the adding CPU 267
8.2.4 Design of datapath 268
8.2.5 Control part design 269
8.2.6 Adding CPU Verilog description 270
8.2.7 Testing adding CPU 275
8.3 CPU Design and Test 281
8.3.1 Details of processor functionality 281
8.3.2 SAYEH datapath 283
8.3.3 SAYEH Verilog description 287
8.3.4 SAYEH top-level testbench 298
8.3.5 Sorting test program 304
8.3.6 SAYEH hardware realization 304
8.4 Summary 306
Problems 306
Suggested Reading 307
Appendix A. List of Keywords 309
Appendix B. Frequently Used System Tasks and Functions 311
Appendix C. Compiler Directives 319
Appendix D. Verilog Formal Syntax Definition 321
Appendix E. Verilog Assertion Monitors 345
Index 375

Verilog Digital System Design.2007

[ 本帖最后由 drjiachen 于 2008-11-11 17:00 编辑 ]

看看！！！！！！！！！：21de

刚刚装了xilink选了VHDL，不知道还能不能改verilog？：9de

容量不小!:11bb :27bb :29bb :30bb :31bb

好东西，下来学习之！

好东西，下来学习之！谢谢！！

好小啊, 是全书么,不管了先看看

一共几个附件啊