PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief: PCB_HANDBOOK.part1.rar

CONTENTS
List of Contributors xxxvii
Preface xxxix
Part 1 Introduction to Printed Circuits
Chapter 1. Electronic Packaging and High-Density Interconnectivity 1.3
1.1 Introduction / 1.3
1.2 Measuring the Interconnectivity Revolution (HDI) / 1.3
1.2.1 Interconnect Density Elements / 1.4
1.2.2 Interconnect Technology Map / 1.4
1.2.3 An Example of the Interconnect Revolution / 1.5
1.2.4 Region of Advanced Technologies / 1.6
1.3 Hierarchy of Interconnections / 1.6
1.4 Factors Affecting Selection of Interconnections / 1.7
1.4.1 Speed of Operation / 1.7
1.4.2 Power Consumption / 1.8
1.4.3 Thermal Management / 1.8
1.4.4 Electronic Interference / 1.8
1.4.5 System Operating Environment / 1.9
1.5 ICs and Packages / 1.10
1.5.1 IC Packages / 1.10
1.5.2 Direct Chip Attach / 1.12
1.5.3 Chip-Scale Packages (CSPs) / 1.13
1.6 Density Evaluations / 1.14
1.6.1 Component Density Analysis / 1.14
1.6.2 PWB Density Metrics / 1.14
1.6.3 Special Metrics for Direct Chip Attach (DCA) / 1.15
1.7 Methods to Increase PWB Density / 1.16
1.7.1 Effect of Pads on Wiring Density / 1.17
1.7.2 Reduction of Conductor Width / 1.18
1.7.3 Effect of Conductor Widths on Board Yields / 1.19
1.7.4 Increase in Number of Conductor Layers / 1.21
References / 1.21
Chapter 2. Semiconductor Packaging Technology 2.1
2.1 Introduction / 2.1
2.1.1 Packaging and Printed Circuit Technology Relationships / 2.3
2.1.2 Electronic Packaging Issues and Concerns / 2.4
2.1.3 Requirements for Electronic Systems / 2.5
2.2 Single-Chip Packaging / 2.5
2.2.1 Dual Inline Packages (DIPs) / 2.6
2.2.2 Leadless Ceramic Chip Carriers / 2.6
2.2.3 Plastic Quad Flat Package (PQFP) / 2.7
2.2.4 Pin Grid Array (PGA) and Pad Array Carrier (PAC) / 2.8
2.2.5 Direct Chip Attach (DCA) / 2.12
v
2.3 Multichip Packages / 2.15
2.3.1 Multichip vs. Single-Chip Packages / 2.15
2.3.2 MCPs Using Printed Circuit Technology / 2.16
2.3.3 MCP s Using Organic Substrates / 2.16
2.3.4 MCP and PGA / 2.17
2.3.5 Multichip Stacked-Die Packages / 2.17
2.3.6 MCP and Known Good Die / 2.17
2.3.7 System-in-a-Package / 2.18
2.4 Optical Interconnects / 2.18
2.4.1 Components and Packages / 2.20
2.4.2 Advantages of Optical Interconnects / 2.21
2.5 High-Density/High-Performance Packaging Summary / 2.21
2.6 Roadmap Information / 2.21
References / 2.21
Chapter 3. Advanced Packaging 3.1
3.1 Introduction / 3.1
3.1.1 Package Drivers / 3.1
3.1.2 Packaging as a Basic Design Element / 3.2
3.2 System-on-a-Chip (SOC) vs. System-on-a-Package (SOP) / 3.3
3.2.1 SOC / 3.3
3.2.2 SOP / 3.4
3.3 Multichip Modules / 3.5
3.3.1 MCM-D / 3.7
3.3.2 MCM-C / 3.9
3.3.3 MCM-L / 3.11
3.3.4 MCM-D/C / 3.13
3.3.5 MCM-D/L / 3.13
3.4 Multichip Packaging / 3.14
3.4.1 Few-Chip Packaging (FCP) / 3.14
3.4.2 Partitioned Silicon (Tiling) / 3.15
3.4.3 Chip-Scale Packaging (CSP) / 3.16
3.4.4 Wafer-Scale Integration (WSI) / 3.17
3.4.5 Three-Dimensional (3-D) Packaging / 3.17
3.5 Enabling Technologies / 3.19
3.5.1 Known Good Die (KGD) / 3.19
3.5.2 Chip Thinning / 3.19
3.5.3 Chip Attach / 3.20
3.5.4 Chip-on-Board (COB) / 3.21
3.5.5 Passive Devices / 3.23
3.6 Drivers for Advanced Packaging / 3.25
3.6.1 Materials / 3.26
3.6.2 Lead-Free / 3.26
3.6.3 Micro-Electro-Mechanical and Micro-Opto-Electro-Mechanical Systems / 3.26
3.6.4 Technology Developments and Trends / 3.27
References / 3.28
Chapter 4. Types of Printed Wiring Boards 4.1
4.1 Introduction / 4.1
4.2 Classification of Printed Wiring Boards / 4.1
4.2.1 Basic PWB Classifications / 4.1
4.3 Organic and Nonorganic Substrates / 4.3
4.3.1 Organic Substrates / 4.3
4.3.2 Nonorganic Substrates / 4.3
4.4 Graphical and Discrete-Wire Boards / 4.3
4.4.1 Graphical Interconnection Board / 4.3
4.4.2 Discrete-Wire Boards / 4.4
vi CONTENTS
4.5 Rigid and Flexible Boards / 4.5
4.6 Graphically Produced Boards / 4.6
4.6.1 Single-Sided Boards (SSBs) / 4.6
4.6.2 Double-Sided Boards / 4.7
4.6.3 Multilayer Boards (MLBs) / 4.8
4.7 Molded Interconnection Devices / 4.10
4.8 Plater-Through-Hold (PTH) Technologies / 4.10
4.8.1 Subtractive and Additive Processes / 4.10
4.8.2 Pattern Plating / 4.11
4.8.3 Panel Plating / 4.13
4.8.4 Additive Plating / 4.13
4.9 Summary / 4.13
References / 4.14
Part 2 Materials
Chapter 5. Introduction to Base Materials 5.3
5.1 Introduction / 5.3
5.2 Grades and Specifications / 5.3
5.2.1 NEMA and IPC Grades / 5.3
5.2.2 Glass Transition Temperature / 5.4
5.3 NEMA Industrial Laminating Thermosetting Products / 5.7
5.4 IPC-4101 Specification for Base Materials for Rigid and Multilayer Printed Boards / 5.9
5.5 FR-4 Issues / 5.9
5.5.1 The Many Faces of FR-4 / 5.9
5.5.2 The Longevity of FR-4 / 5.9
5.6 Laminate Identification Scheme / 5.10
5.7 Prepreg Identification Scheme / 5.13
References / 5.14
Chapter 6. Base Material Components 6.1
6.1 Introduction / 6.1
6.2 Epoxy Resin Systems / 6.1
6.2.1 Definition of Epoxy / 6.1
6.2.2 Difunctional Epoxies / 6.2
6.2.3 Tetrafunctional and Multifunctional Epoxies / 6.3
6.3 Other Resin Systems / 6.3
6.3.1 Epoxy Blends / 6.4
6.3.2 Bismaleimide Triazine (BT)/Epoxy / 6.4
6.3.3 Cyanate Ester / 6.4
6.3.4 Polyimide / 6.4
6.3.5 Polyester / 6.5
6.3.6 Polytetrafluoroethylene (PTFE,Teflon? / 6.5
6.3.7 Allylated Polyphenylene Ether (APPE) / 6.5
6.4 Additives / 6.5
6.4.1 Curing Agents and Accelerators / 6.5
6.4.2 Flame Retardants / 6.5
6.4.3 Ultraviolet (UV) Blockers/Fluorescing Aids / 6.6
6.5 Reinforcements / 6.6
6.5.1 Woven Fiberglass / 6.6
6.5.2 Yarn Nomenclature / 6.8
6.5.3 Fiberglass Cloths / 6.9
6.5.4 Other Reinforcements / 6.10
6.6 Conductive Materials / 6.11
6.6.1 Electrodeposited Copper Foil / 6.12
CONTENTS vii
6.6.2 Reverse-Treated Foils / 6.14
6.6.3 Wrought Annealed Copper Foils / 6.15
6.6.4 Other Foil Types / 6.16
References / 6.16
Chapter 7. Base Material Manufacturing Processes 7.1
7.1 Laminate and Prepreg Manufacturing Processes / 7.1
7.2 Conventional Manufacturing Processes / 7.1
7.2.1 Prepreg Manufacturing / 7.1
7.2.2 Laminate Manufacturing / 7.3
7.3 Direct-Current or Continuous-Foil Manufacturing / 7.6
7.4 Continuous Manufacturing Processes / 7.7
References / 7.7
Chapter 8. Properties of Base Materials 8.1
8.1 Introduction / 8.1
8.2 Thermal, Physical, and Mechanical Properties / 8.1
8.2.1 Coefficient of Thermal Expansion (CTE) / 8.1
8.2.2 Time to Delamination / 8.3
8.2.3 Decomposition Temperature / 8.3
8.2.4 Arc Resistance / 8.3
8.2.5 Density / 8.4
8.2.6 Copper Peel Strength / 8.4
8.2.7 Flexural Strength / 8.5
8.2.8 Water and Moisture Absorption / 8.5
8.2.9 Chemical Resistance / 8.6
8.2.10 Flammability / 8.6
8.3 Electrical Properties / 8.7
8.3.1 Dielectric Constant or Permittivity / 8.7
8.3.2 Dissipation Factor or Loss Tangent (Tan ? / 8.8
8.3.3 Insulation Resistance / 8.8
8.3.4 Volume Resistivity / 8.8
8.3.5 Surface Resistivity / 8.8
8.3.6 Electrical Strength / 8.9
8.3.7 Dielectric Breakdown / 8.9
References / 8.9
Chapter 9. Densification Issues for Base Materials 9.1
9.1 Impact of Trends in IC Technology and PCB Design / 9.1
9.2 Methods of Increasing Circuit Density / 9.2
9.3 Copper Foil / 9.2
9.3.1 HTE Foil / 9.2
9.3.2 Low-Profile and Reverse-Treated Copper Foils / 9.2
9.3.3 Thin Copper Foils / 9.3
9.3.4 Foils for High-Performance Resin Systems / 9.4
9.4 Dimensional Stability / 9.4
9.4.1 A Model of Printed Circuit Registration Capability / 9.4
9.4.2 Dimensional Stability Test Methods / 9.5
9.4.3 Improving Dimensional Stability / 9.5
9.5 Thermal Properties and Reliability / 9.6
9.5.1 Reliability Testing / 9.6
9.5.2 Conductive Anodic Filament (CAF) Growth / 9.7
9.5.3 Choosing a Base Material / 9.7
9.6 Electrical Properties / 9.8
9.6.1 Importance of These Properties / 9.8
9.6.2 Choosing a Base Material / 9.9
9.7 High-Density Interconnect/Microvia Materials / 9.12
viii CONTENTS
9.8 Integrated Passives / 9.13
9.8.1 Buried Capacitance / 9.13
9.8.2 Buried Resistors / 9.14
References / 9.14
Chapter 10. Introducing Base Materials into the PCB Manufacturing Process 10.1
10.1 Introduction / 10.1
10.2 Validation of Physical,Thermal, and Electrical Properties / 10.1
10.3 Laminate Constructions / 10.2
10.3.1 Single-Ply vs. Multiple-Ply Constructions / 10.2
10.3.2 Resin Contents / 10.3
10.3.3 Laminate Flatness and Flexural Strength / 10.3
10.4 Prepreg Options and Yield per Ply Values / 10.3
10.5 Multilayer Press Cycle Qualification / 10.3
10.6 Prepreg-to-Innerlayer Circuit Adhesion / 10.5
10.7 Dimensional Stability Characterizations / 10.6
10.8 Impedance Characterizations / 10.6
10.9 Drilling Optimization / 10.6
10.10 Desmearing and Electroless Copper Deposition Characteristics / 10.8
10.11 Absorption of Ultraviolet Light / 10.9
10.12 Fluorescence at Automatic Optical Inspection / 10.9
References / 10.10
Chapter 11. HDI Microvia Materials 11.1
11.1 Introduction / 11.1
11.2 Definitions / 11.1
11.3 Technology Considerations for HDI Microvia Fabrication / 11.1
11.3.1 Laser Via Formation / 11.2
11.3.2 Etching-Process-Formed Vias / 11.3
11.3.3 Photovia Formation / 11.4
11.3.4 Dry Metallization (Conductive Inks/Conductive Paste/Insulation Displacement) / 11.5
11.4 Alternative HDI Constructions for Improved Area Utilization / 11.5
11.4.1 ALIVH?/ 11.5
11.4.2 B2it / 011.6
11.5 Materials for HDI Microvia Fabrication / 11.7
11.5.1 Copper-Clad Dielectric Materials / 11.7
11.5.2 Unclad Dielectric Materials / 11.8
11.5.3 Clad vs. Unclad Dielectric Materials / 11.9
11.6 Material and Technology Drivers / 11.10
11.7 Examples of HDI Microvia Organic Substrates / 11.11
11.7.1 Nonreinforced Dielectric Materials / 11.12
11.7.2 Aramid-Reinforced, Nonwoven, Nonglass Laminate / 11.15
11.8 Via Filling / 11.17
11.8.1 Basics / 11.17
11.8.2 Screen-Printed Via-Filling Materials / 11.18
11.9 Acknowledgments / 11.19
References / 11.20
Chapter 12. Laminate Qualification and Testing 12.1
12.1 Introduction / 12.1
12.2 Industry Standards / 12.1
12.2.1 IPC-TM-650 / 12.2
12.2.2 IPC Specification Sheets / 12.2
12.2.3 American Society for Testing and Materials (ASTM) / 12.2
12.2.4 National Electrical Manufacturers Association (NEMA) / 12.2
12.2.5 NEMA Grades / 12.3
CONTENTS ix
12.3 Laminate Test Strategies / 12.3
12.3.1 Data Comparison / 12.4
12.3.2 Two-Tier Strategy Approach / 12.4
12.4 Initial Tests / 12.4
12.4.1 Surface and Appearance / 12.4
12.4.2 Copper Peel Strength / 12.5
12.4.3 Solder Shock / 12.6
12.4.4 Glass Transition Temperature Tg / 12.6
12.5 Full Material Characterization / 12.6
12.5.1 Mechanical Tests / 12.7
12.5.2 Thermomechanical Tests / 12.9
12.5.3 Electrical Characterization / 12.16
12.5.4 Other Laminate Properties / 12.18
12.6 Characterization Test Plan / 12.19
12.7 Manufacturability in the Shop / 12.20
Part 3 Engineering and Design
Chapter 13. Physical Characteristics of PCB 13.3
13.1 Classes of PCB Designs / 13.3
13.1.1 Characteristics of Analog, RF, and Microwave PCBs / 13.3
13.1.2 Characteristics of Digital-Based PCBs / 13.6
13.2 Types of PCBs or Packages for Electronic Circuits / 13.9
13.2.1 Single- and Double-Sided PCBs / 13.9
13.2.2 Multilayer PCBs / 13.10
13.2.3 Discrete-Wire or Multiwire PCBs / 13.10
13.2.4 Hybrids / 13.10
13.2.5 Flexible Circuits / 13.10
13.2.6 Flexible Rigid or Flex-Rigid / 13.12
13.2.7 Backplanes / 13.12
13.2.8 MCMs (Multichip Modules) / 13.12
13.3 Methods of Attaching Components / 13.14
13.3.1 Through-Hole Only / 13.14
13.3.2 Through-Hole Mixed with Surface-Mount / 13.14
13.3.3 Surface-Mount, One Side Only / 13.14
13.3.4 Surface-Mount, Both Sides / 13.14
13.3.5 Surface-Mount, Both Sides with Through-Hole / 13.14
13.4 Component Package Types / 13.15
13.4.1 Through-Hole / 13.15
13.4.2 Surface Mount / 13.15
13.4.3 Fine Pitch / 13.16
13.4.4 Press Fit / 13.16
13.4.5 TAB / 13.16
13.4.6 Flip Chip / 13.17
13.4.7 BGA / 13.17
13.4.8 Wire-Bonded Bare Die / 13.17
13.5 Materials Choices / 13.18
13.5.1 Reinforcement Materials / 13.19
13.5.2 Polyimide Resin Systems / 13.20
13.5.3 Epoxy-Based Resin Systems / 13.20
13.5.4 Cyanate Ester-Based Resin Systems / 13.20
13.5.5 Ceramics / 13.20
13.5.6 Exotic Laminates / 13.20
13.5.7 Embedded Components Materials / 13.21
13.6 Fabrication Methods / 13.22
13.6.1 Punch Forming / 13.22
13.6.2 Roll Forming / 13.22
x CONTENTS
13.6.3 Lamination / 13.23
13.6.4 Subtractive Plating / 13.23
13.6.5 Additive Plating / 13.23
13.6.6 Discrete Wire / 13.23
13.7 Choosing a Package Type and Fabrication Vendor / 13.24
13.7.1 Trading Off Number of Layers Against Area / 13.24
13.7.2 One PCB vs. Multiple PCBs / 13.25
Chapter 14. The PCB Design Process 14.1
14.1 Objective of the PCB Design Process / 14.1
14.2 Design Processes / 14.1
14.2.1 The System Specification / 14.1
14.2.2 System Block Diagram / 14.2
14.2.3 Partitioning System into PCBs / 14.2
14.2.4 Determining PCB Size / 14.2
14.2.5 Creating the Schematic / 14.2
14.2.6 Building Component Libraries / 14.3
14.2.7 Simulating Design / 14.3
14.2.8 Placing Components on PCBs / 14.4
14.2.9 Sequencing Nets to High-Speed Rules / 14.4
14.2.10 Simulating Timing and Transmission Lines Effects / 14.4
14.2.11 Adjusting Sequencing and Placement / 14.4
14.2.12 Testing Routability of Placement / 14.4
14.2.13 Routing PCB / 14.5
14.2.14 Checking Routed Results / 14.5
14.2.15 Generating Manufacturing Files / 14.5
14.2.16 Archiving Design / 14.5
14.3 Design Tools / 14.6
14.3.1 CAE Tools / 14.6
14.3.2 CAD Tools / 14.8
14.3.3 CAM Tools / 14.10
14.4 Selecting a Set of Design Tools / 14.10
14.4.1 Specification / 14.10
14.4.2 Supplier Survey / 14.11
14.4.3 Benchmarking / 14.11
14.4.4 Multiple Tools / 14.11
14.5 Interfacing CAE, CAD, and CAM Tools to Each Other / 14.11
14.6 Inputs to the Design Process / 14.11
14.6.1 Libraries / 14.11
14.6.2 PCB Characteristics / 14.12
14.6.3 Spacing and Width Rules / 14.12
14.6.4 Netlists / 14.12
14.6.5 Parts Lists / 14.12
Chapter 15. Electrical and Mechanical Design Parameters 15.1
15.1 Printed Circuit Design Requirements / 15.1
15.2 Introduction to Electrical Signal Integrity / 15.1
15.2.1 Drivers for Electrical Signal Integrity / 15.1
15.2.2 Analog Electrical Signal Integrity / 15.2
15.2.3 Digital Electrical Signal Integrity / 15.3
15.3 Introduction to Electromagnetic Compatibility / 15.3
15.4 Noise Budget / 15.4
15.5 Designing for Signal Integrity and Electromagnetic Compatibility / 15.4
15.5.1 High Speed and High Frequency / 15.4
15.5.2 Leakage Currents and Voltages / 15.5
15.5.3 Voltage and Ground Distribution Concepts / 15.6
CONTENTS xi
15.6 Mechanical Design Requirements / 15.9
15.6.1 General Mechanical Design Requirements / 15.10
15.6.2 Shock and Vibration / 015.12
15.6.3 Methods of Reinforcement and Snubbers / 15.17
References / 15.17
Chapter 16. Controlled Impedance 16.1
16.1 Introduction / 16.1
16.1.1 Definitions / 16.1
16.1.2 The Digital Signal (Pulse) / 16.1
16.1.3 Controlled-Impedance Needs / 16.2
16.2 Basic Impedance Mismatch Effects / 16.3
16.2.1 Signal Reflection Process / 16.3
16.2.2 Effect of Signal Frequency / 16.3
16.2.3 Effect of Components on Circuit Consistency / 16.4
16.3 Impedance / 16.4
16.3.1 Factors Determining Impedance / 16.4
16.3.2 Characteristic Impedance / 16.5
16.4 Transmission Lines / 16.5
16.4.1 Single-Ended Transmission Line / 16.5
16.4.2 Differential Transmission Line / 16.5
16.5 Transmission Line Implementation in a PCB / 16.6
16.5.1 Dimensions / 16.6
16.5.2 Factors of Influence / 16.7
16.5.3 Single-Ended Examples / 16.8
16.5.4 Differential Examples / 16.11
16.6 Calculation of PCB Track Impedance / 16.15
16.6.1 Microstrip Example / 16.15
16.6.2 Algebraic Equations / 16.17
16.6.3 Numerical Principles / 16.18
16.6.4 Numerical Results / 16.20
16.6.5 Practical Results / 16.22
16.7 Results Discussion / 16.22
16.8 Use of Personal Computers for Calculations / 16.23
References / 16.24
Chapter 17. Multilayer Design Issues 17.1
17.1 Reliability Issues / 17.1
17.1.1 Substrate Flaws / 17.2
17.1.2 Copper Surface Damage / 17.5
17.1.3 Mechanical Problems / 17.6
17.1.4 Internal Misregistration / 17.9
17.1.5 Connection Flaws / 17.16
17.2 Electrical Performance / 17.18
17.2.1 Controlled Impedance (CI) / 17.19
17.2.2 Signal Attenuation at High Frequency / 17.19
17.2.3 Signal Coupling at High Frequencies / 17.20
Chapter 18. Planning for Design, Fabrication, and Assembly 18.1
18.1 Introduction / 18.1
18.1.1 Design Planning and Predicting Cost / 18.1
18.1.2 Design Planning and Manufacturing Planning / 18.2
18.2 General Considerations / 18.2
18.2.1 Planning Elements / 18.2
18.2.2 Planning Concepts / 18.3
18.2.3 Producibility / 18.3
xii CONTENTS
18.3 New Product Design / 18.4
18.3.1 Expanded Design Process / 18.4
18.3.2 Product Definition / 18.4
18.3.3 Metrics for Predicting and Planning Producibility / 18.6
18.3.4 Nonmetrics / 18.7
18.3.5 Figure of Merit (FOM) Metric / 18.8
18.3.6 Figure of Merit Linear Equation / 18.9
18.4 Layout Trade-Off Planning / 18.11
18.4.1 Balancing the Density Equation / 18.11
18.4.2 Wiring Demand Wd / 18.12
18.4.3 Wiring Capacity Wc / 18.13
18.4.4 Layout Efficiency / 18.13
18.4.5 Selecting Design Rules / 18.14
18.4.6 Typical Example of Wiring Demand Calculation / 18.18
18.5 PWB Fabrication Trade-Off Planning / 18.18
18.5.1 Fabrication Complexity Matrix / 18.18
18.5.2 Predicting Producibility / 18.19
18.5.3 Example of a Complete PWB Complexity Matrix / 18.21
18.6 Assembly Trade-Off Planning / 18.23
18.6.1 Assembly Complexity Matrix / 18.23
18.6.2 Example of an Assembly Complexity Matrix / 18.24
18.7 Tools for Audits / 18.25
18.7.1 Manufacturability Audits Performed by the Designer / 18.25
References / 18.28
Chapter 19. Manufacturing Information Documentation and Transfer 19.1
19.1 Introduction / 19.1
19.2 Information Transfer / 19.1
19.2.1 Information Required / 19.2
19.2.2 Modem Transmission / 19.3
19.2.3 Internet Transmission / 19.3
19.3 Initial Design Review / 19.4
19.3.1 Design Review / 19.4
19.3.2 Material Requirements / 19.6
19.3.3 Process Requirements / 19.7
19.3.4 Panelization / 19.9
19.3.5 Initial Design Analysis / 19.10
19.4 Design Input / 19.11
19.5 Design Analysis and Review / 19.11
19.5.1 Design Rule Checking / 19.11
19.5.2 Manufacturability Review / 19.16
19.5.3 Single Image Edits / 19.16
19.5.4 DFM Enhancements / 19.16
19.6 Panelization Process / 19.18
19.7 Additional Processes / 19.18
Chapter 20. Electronic Contract Manufacturing Supplier Selection
and Management 20.1
20.1 Introduction / 20.1
20.1.1 Development of the Electronic Manufacturing Services Industry / 20.1
20.2 Business Plan / 20.2
20.2.1 Customer Requirements桭ive Stages of Product Life / 20.2
20.2.2 Supplier Requirements / 20.3
20.2.3 Presenting the Corporate Goals and Objectives / 20.3
20.2.4 Business Plan / 20.4
20.3 Supplier Capabilities / 20.4
20.3.1 Overall Capabilities / 20.4
CONTENTS xiii
20.3.2 Services Offered / 20.5
20.3.3 Support Services / 20.6
20.3.4 Technical Capability / 20.7
20.4 Supplier Qualification / 20.8
20.5 Time-to-Market Elements / 20.8
20.5.1 Specific Elements: Descriptions and Time Requirements / 20.8
20.6 Quality System / 20.11
20.6.1 Total Quality Management / 20.11
20.6.2 ISO 9000 / 20.11
20.7 Request for Quotation / 20.11
20.7.1 Purpose / 20.11
20.7.2 Contents and Sample / 20.11
20.7.3 Responses Required / 20.13
20.8 Managing the Relationship / 20.13
20.8.1 Getting Started / 20.13
20.8.2 Evaluating Performance: Customer Satisfaction Survey (CSS) / 20.15
Part 4 High-Density Interconnect
Chapter 21. Introduction to High-Density Interconnection Technology 21.3
21.1 High-Density Interconnects (HDIs) Defined / 21.3
21.1.1 HDI Characterization / 21.3
21.1.2 Advantages and Benefits / 21.4
21.1.3 Comparison of HDIs and Traditional Printed Wiring Boards / 21.5
21.1.4 Design/Cost/Performance Trade-offs / 21.5
21.1.5 Specifications and Standards / 21.6
21.2 HDI Structures / 21.6
21.2.1 Construction Types / 21.8
21.2.2 Design Rules and Categories / 21.9
21.3 Design of HDI Boards / 21.10
21.3.1 Design Tools / 21.11
21.3.2 Trade-off Analysis / 21.11
21.4 Materials / 21.12
21.4.1 HDI Material Requirements / 21.12
21.4.2 Copper-Clad Dielectrics / 21.13
21.4.3 Unclad Nonreinforced Dielectric / 21.16
References / 21.17
Chapter 22. High-Density Interconnect-Build-up Technologies 22.1
22.1 Introduction to High-Density Interconnect Substrates / 22.1
22.2 Build-up Technologies / 22.1
22.2.1 Mechanical Drilling / 22.2
22.2.2 Photosensitive Dielectrics / 22.2
22.2.3 Laser Drilling / 22.4
22.2.4 Plasma Etching / 22.5
22.2.5 Insulation Displacement / 22.5
22.3 Photodefined Via Technologies / 22.6
22.3.1 Photoimageable Dielectric Technology / 22.6
22.3.2 IPN Polymer Build-up Structure System / 22.9
22.3.3 Carrier-Formed Circuits / 22.9
22.4 Laser-Generated Vias / 22.10
22.4.1 Laser-Formed Blind/Through-Vias / 22.10
22.4.2 Laser-Drilled Flex (ViaThin) / 22.11
22.4.3 High-Density Interconnects / 22.12
22.5 Chemical/Metallurgical Bonded Via in PWB Technologies / 22.13
22.5.1 Paste-Bonded Solid-Via Laminate (ALIVH) / 22.13
xiv CONTENTS
22.5.2 Co-lamination with Conductive Paste/Adhesive Structures / 22.14
22.5.3 Microfilled Via Technology (MfVia? / 22.16
22.5.4 Transient Liquid Phase Sintering (TLPS) Conductive Circuits / 22.17
22.6 Wet/Dry-Etched Vias / 22.18
22.6.1 DYCOstrate / 22.18
22.6.2 Plasma-Etched Redistribution Layers (PERL) / 22.20
22.7 Insulation Displacement Technology / 22.22
22.7.1 Buried Bump Interconnect (BbiT) / 22.22
22.8 Imprinted Circuits / 22.23
References / 22.23
Chapter 23. Microvia Hole Technologies 23.1
23.1 Introduction / 23.1
23.2 Definitions / 23.1
23.3 Dielectric Materials and Coating Methods / 23.3
23.4 Photovia Materials / 23.3
23.5 Laser Via Materials / 23.4
23.6 Plasma Via Materials / 23.6
23.7 Paste Via Materials / 23.6
23.8 Manufacturing Processes / 23.6
23.8.1 Photovia Process / 23.7
23.8.2 Plasma Via Process / 23.8
23.8.3 Laser Via Process / 23.9
23.9 Multiple Layers of Microvia Holes / 23.12
23.10 Other Microvia Technologies / 23.13
23.10.1 ALIVH / 23.13
23.10.2 B2it / 23.14
23.10.3 Other Microvia Processes / 23.15
23.11 Technology Drivers / 23.15
References / 23.15
Part 5 Fabrication Processes
Chapter 24. Drilling Processes 24.3
24.1 Introduction / 24.3
24.2 Materials / 24.4
24.2.1 Laminate Material / 24.4
24.2.2 Drill Bits / 24.5
24.2.3 Drill Bit Rings / 24.8
24.2.4 Entry Material / 24.9
24.2.5 Backup Material / 24.9
24.2.6 Tooling Pins / 24.10
24.3 Machines / 24.11
24.3.1 Air / 24.11
24.3.2 Vacuum / 24.12
24.3.3 Tooling / 24.12
24.3.4 Spindles / 24.12
24.3.5 Mechanical Factors / 24.14
24.3.6 Surfaces / 24.14
24.4 Methods / 24.15
24.4.1 Surface Speed and Spindle Speed / 24.15
24.4.2 Chip Load and Infeed Rate / 24.16
24.4.3 Retract Rate / 24.16
24.4.4 Backup Penetration Depth / 24.16
24.4.5 Hits per Tool / 24.17
CONTENTS xv
24.4.6 Stack Clearance Height / 24.17
24.4.7 Drilled Stack Height / 24.18
24.4.8 Stacking and Pinning / 24.18
24.5 Hole Quality / 24.18
24.5.1 Definition of Terms / 24.18
24.5.2 Examples of Drilled Hole Defects / 24.19
24.6 Postdrilling Inspection / 24.20
24.7 Drilling Cost per Hole / 24.20
24.7.1 Machine Time / 24.20
24.7.2 Drill Bits / 24.22
24.7.3 Entry and Backup Materials / 24.22
24.7.4 Burden and Labor / 24.22
24.7.5 Total Drilling Cost and Cost per Hole / 24.22
Chapter 25. High-Density Interconnect Drilling 25.1
25.1 Introduction / 25.1
25.2 Factors Affecting High-Density Drilling / 25.1
25.2.1 Positioning/Hole Location / 25.2
25.2.2 Predrilling Issues / 25.2
25.2.3 Drill Room Temperature and Relative Humidity / 25.2
25.2.4 Vacuum / 25.3
25.2.5 Drill Bit Condition / 25.4
25.2.6 Dynamic Spindle Run-out / 25.4
25.2.7 Spindle Speed / 25.4
25.2.8 Retraction Rate / 25.6
25.3 Depth-Controlled Drilling Methods / 25.6
25.3.1 Manual Through-Hole Drilling / 25.6
25.3.2 Depth-Controlled Drilling / 25.6
25.3.3 Controlled-Penetration Drilling / 25.7
25.4 High-Aspect-Ratio Drilling / 25.7
25.4.1 Peck Drilling / 25.7
25.4.2 Pulse Drilling / 25.9
Chapter 26. Imaging 26.1
26.1 Introduction / 26.1
26.2 Photosensitive Materials / 26.2
26.2.1 Positive- and Negative-Acting Systems / 26.2
26.2.2 Decision Factors / 26.3
26.3 Dry-Film Resists / 26.4
26.3.1 Chemical Composition Overview / 26.5
26.3.2 Aqueous-Processable Dry Films / 26.5
26.3.3 Semiaqueous- and Solvent-Developable Dry Films / 26.6
26.4 Liquid Photoresists / 26.7
26.4.1 Negative-Acting Liquid Photoresists / 26.7
26.4.2 Positive-Acting Liquid Photoresists / 26.7
26.5 Electrophoretic Depositable Photoresists / 26.7
26.6 Resist Processing / 26.8
26.6.1 Cleanliness Considerations / 26.8
26.6.2 Surface Preparation / 26.9
26.6.3 Photoresist Application / 26.11
26.6.4 Expose / 26.16
26.6.5 Develop / 26.26
26.6.6 Strip / 26.27
26.7 Design for Manufacturing / 26.27
26.7.1 Process Sequence: Etching vs. Plating Considerations / 26.27
xvi CONTENTS
26.7.2 Line and Space Division for a Fixed Pitch / 26.28
26.7.3 PTH Capture Pad Size and Shape for Optimum Line Formation / 26.28
References / 26.29
Chapter 27. Multilayer Materials and Processing 27.1
27.1 Introduction / 27.1
27.2 Multilayer Printed Wiring Board Materials / 27.2
27.2.1 Critical Properties / 27.2
27.2.2 Standard Properties of the Epoxy Systems / 27.4
27.2.3 Materials with Enhanced Thermal Properties / 27.4
27.2.4 Materials with Enhanced Electrical Properties / 27.6
27.2.5 Materials Summary / 27.8
27.3 Multilayer Construction Types / 27.8
27.3.1 IPC Classifications / 27.8
27.3.2 Basic Type 3 ML-PWB Stack-ups / 27.10
27.3.3 Sequential Laminations / 27.14
27.3.4 The Buried Via Stack-up / 27.15
27.3.5 The Blind Via Stack-up / 27.16
27.3.6 The High-Density Stack-up / 27.18
27.4 ML-PWB Processing and Flows / 27.21
27.4.1 Process Flow Charts / 27.21
27.4.2 Innerlayer Materials / 27.22
27.4.3 Innerlayer Process / 27.25
27.4.4 ML-PWB Tooling / 27.26
27.4.5 Tooling Hole Formation / 27.27
27.4.6 Tooling System / 27.28
27.4.7 Imaging / 27.29
27.4.8 Develop, Etch, and Strip / 27.31
27.4.9 Inspection / 27.31
27.4.10 Adhesion Promotion / 27.32
27.4.11 Drilling / 27.33
27.5 Lamination Process / 27.34
27.5.1 Layup and Materials / 27.34
27.5.2 Lamination Stack-up / 27.35
27.5.3 Lamination Process Methods / 27.36
27.5.4 Critical Lamination Variables / 27.37
27.5.5 Critical B-Stage Variables / 27.38
27.5.6 Buried and Blind Via Considerations / 27.38
27.6 Lamination Process Control and Troubleshooting / 27.39
27.7 Lamination Overview / 27.41
27.8 ML-PWB Summary / 27.41
Chapter 28. Preparing Boards for Plating 28.1
28.1 Introduction / 28.1
28.2 Process Designs / 28.1
28.2.1 Facility Considerations / 28.1
28.2.2 Process Considerations / 28.2
28.3 Process Feedwater / 28.3
28.3.1 Water Supply / 28.3
28.3.2 Water Quality / 28.3
28.3.3 Water Purification / 28.4
28.4 Multilayer PTH Preprocessing / 28.5
28.4.1 Smear Removal / 28.5
28.4.2 Etchback / 28.5
28.4.3 Smear Removal/Etchback Methods / 28.5
28.4.4 Process Outline: Smear Removal and Etchback / 28.6
CONTENTS xvii
28.5 Electroless Copper / 28.7
28.5.1 Purpose / 28.7
28.5.2 Mechanism / 28.8
28.5.3 Electroless Copper Processes / 28.8
28.5.4 Process Outline / 28.9
References / 28.10
Chapter 29. Electroplating 29.1
29.1 Introduction / 29.1
29.2 Electroplating Basics / 29.1
29.3 Horizontal Electroplating / 29.2
29.3.1 Advantages of Horizontal Processing / 29.3
29.3.2 Drawbacks of Horizontal Processing / 29.4
29.4 Copper Electroplating General Issues / 29.4
29.4.1 Pattern Plating vs. Panel Plating / 29.5
29.4.2 Thickness Distribution / 29.5
29.4.3 Additives in Acid Copper Plating / 29.5
29.4.4 Carrier/Suppressor / 29.7
29.4.5 Additive/Brightener / 29.8
29.4.6 Levelers / 29.8
29.4.7 Low-Current-Density Plating / 29.9
29.4.8 Chemically Mediated Process / 29.9
29.4.9 Pulse Plating (Electrically Mediated Process) / 29.10
29.4.10 Key Factors for Uniform Plating / 29.11
29.5 Acid Copper Sulfate Solutions and Operation / 29.12
29.5.1 Solution Makeup by Current Density / 29.12
29.5.2 Operation and Control / 29.12
29.5.3 Process Controls / 29.13
29.5.4 Cross-Sectioning Results桾roubleshooting / 29.14
29.5.5 Inferior Copper Deposits / 29.14
29.6 Solder (Tin-Lead) Electroplating / 29.15
29.6.1 Agitation / 29.17
29.6.2 Filtration / 29.18
29.6.3 Carbon Treatment / 29.18
29.6.4 Contaminations / 29.18
29.6.5 Solution Controls / 29.18
29.6.6 Deposition Rate / 29.19
29.6.7 Deposit Composition / 29.19
29.6.8 Hull Cell / 29.19
29.6.9 Visual Observation of Plating / 29.19
29.6.10 Corrective Actions / 29.19
29.7 Tin Electroplating / 29.20
29.7.1 Acid Tin Sulfate / 29.20
29.7.2 Problems with Tin Electroplating / 29.21
29.8 Nickel Electroplating / 29.21
29.8.1 Nickel Sulfamate / 29.22
29.8.2 Nickel Sulfate / 29.23
29.9 Gold Electroplating / 29.23
29.9.1 Acid Hard Gold / 29.24
29.9.2 Pure 24-Karat Gold / 29.25
29.9.3 Alkaline, Noncyanide Gold / 29.26
29.9.4 Gold Plate Tests / 29.26
29.10 Platinum Metals / 29.26
29.10.1 Rhodium / 29.26
29.10.2 Palladium and Palladium-Nickel Alloys / 29.27
29.10.3 Ruthenium / 29.27
29.11 Silver Electroplating / 29.27
xviii CONTENTS
29.12 Laboratory Process Control / 29.27
29.12.1 Conventional Wet Chemical Analysis / 29.27
29.12.2 Advanced Instrumental Techniques / 29.28
29.12.3 Metallographic Cross-Sectioning / 29.28
29.12.4 Hull Cell / 29.29
References / 29.29
Chapter 30. Direct Plating 30.1
30.1 Direct Metallization Technology / 30.1
30.1.1 Direct Metallization Technologies Overview / 30.1
30.1.2 Palladium-Based Systems / 30.2
30.1.3 Carbon/Graphite Systems / 30.4
30.1.4 Conductive Polymer Systems / 30.6
30.1.5 Other Methods / 30.7
30.1.6 Comparative Steps of DMT Process / 30.8
30.1.7 Horizontal Process Equipment for DMT / 30.10
30.1.8 DMT Process Issues / 30.10
30.1.9 DMT Process Summary / 30.11
References / 30.11
Chapter 31. PWB Manufacture Using Fully Electroless Copper 31.1
31.1 Fully Electroless Plating / 31.1
31.2 The Additive Process and Its Variations / 31.2
31.3 Pattern-Plating Additive / 31.2
31.3.1 Catalytic Laminate with CC-4?/ 31.2
31.3.2 Noncatalytic Laminate with AP-II / 31.5
31.3.3 Foil Process / 31.6
31.4 Panel-Plate Additive / 31.7
31.4.1 Process Steps / 31.7
31.4.2 Process Issues / 31.8
31.5 Partly Additive / 31.8
31.5.1 Process Steps / 31.8
31.5.2 Process Issues / 31.9
31.5.3 Fine-Pitch Components / 31.9
31.6 Chemistry of Electroless Plating / 31.9
31.6.1 Electroless Plating Solution Chemical Reactions / 31.9
31.6.2 Use of Stabilizers / 31.10
31.6.3 Surfactant / 31.11
31.6.4 Reliability of Deposited Copper and Inorganic Compounds / 31.11
31.6.5 Removal of Impurities / 31.11
31.6.6 Environmental Issues of Formaldehyde / 31.12
31.7 Fully Electroless Plating Issues / 31.12
31.7.1 Efficiency of Electroless and Galvanic Plating / 31.12
31.7.2 Photochemical Imaging Systems / 31.12
31.7.3 Molded Circuit Application / 31.12
References / 31.14
Chapter 32. Surface Finishes 32.1
32.1 Introduction / 32.1
32.1.1 Surface Finishes桝lternatives to HASL / 32.1
32.1.2 Surface Finish Capability Summary / 32.2
32.2 Organic Solderability Preservative (OSP) / 32.2
32.2.1 Principles / 32.2
32.2.2 Process / 32.2
CONTENTS xix
32.2.3 Applications / 32.3
32.2.4 Limitations / 32.3
32.3 Electroless Nickel/Immersion Gold (ENIG) / 32.4
32.3.1 Principles / 32.4
32.3.2 Process / 32.4
32.3.3 Applications / 32.5
32.3.4 Limitations / 32.5
32.4 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) / 32.5
32.4.1 Principles / 32.5
32.4.2 Process / 32.6
32.4.3 Applications / 32.7
32.4.4 Limitations / 32.7
32.5 Immersion Silver / 32.7
32.5.1 Principles / 32.7
32.5.2 Process / 32.7
32.5.3 Applications / 32.8
32.5.4 Limitations / 32.8
32.6 Immersion Tin / 32.8
32.6.1 Principles / 32.8
32.6.2 Process / 32.9
32.6.3 Applications / 32.9
32.6.4 Limitations / 32.10
32.7 Surface Finish Attribute and Cost Comparison / 32.10
Chapter 33. Etching Process and Technologies 33.1
33.1 Introduction / 33.1
33.2 General Etching Considerations and Procedures / 33.2
33.2.1 Screened Resists / 33.2
33.2.2 Hole Plugging / 33.2
33.2.3 UV-Cured Screen Resists / 33.2
33.2.4 Photoresists / 33.2
33.2.5 Plated Etch Resists / 33.3
33.3 Resist Removal / 33.4
33.3.1 Screen Resist Removal / 33.4
33.3.2 Photoresist Removal / 33.5
33.3.3 Tin and Tin/Lead Resist Removal / 33.5
33.4 Etching Solutions / 33.6
33.4.1 Alkaline Ammonia / 33.6
33.4.2 Cupric Chloride / 33.10
33.4.3 Sulfuric Acid朒ydrogen / 33.14
33.4.4 Persulfates / 33.16
33.4.5 Ferric Chloride / 33.17
33.4.6 Chromic-Sulfuric Acids / 33.17
33.4.7 Nitric Acid / 33.18
33.5 Other Materials for Board Construction / 33.18
33.6 Metals Other than Copper / 33.19
33.6.1 Aluminum / 33.19
33.6.2 Nickel and Nickel-Based Alloys / 33.19
33.6.3 Stainless Steel / 33.19
33.6.4 Silver / 33.20
33.7 Basics of Etched Line Formation / 33.20
33.7.1 The Image / 33.20
33.7.2 Basics of Processing / 33.21
33.7.3 Trace Shape Development / 33.22
33.7.4 Fine-Line Formation Etching Requirements / 33.24
33.8 Equipment and Techniques / 33.26
33.8.1 Spray Equipment Basics / 33.26
33.8.2 Spray Equipment Options / 33.28
33.8.3 Rinsing / 33.29
References / 33.29
xx CONTENTS
Chapter 34. Solder Resist Material and Processes 34.1
34.1 Introduction and Definition / 34.1
34.2 Functions of a Solder Resist / 34.1
34.3 Design Considerations for Solder Resists / 34.1
34.3.1 Design Goals / 34.1
34.3.2 Design Factors / 34.2
34.4 ANSI/IPC-SM-840 Specification / 34.2
34.5 Solder Resist Selection / 34.3
34.5.1 Temporary Resists / 34.4
34.5.2 Permanent Resists / 34.4
34.5.3 Selection Factors / 34.4
34.6 Solder Mask over Bare Copper (SMOBC) / 34.6
34.7 Cleaning and PWB Preparation Prior to Solder Resist Application / 34.7
34.7.1 Surface Preparation / 34.7
34.8 Solder Resist Applications / 34.8
34.8.1 Screen Printing / 34.8
34.8.2 Liquid Photoprint / 34.8
34.8.3 Dry Film / 34.8
34.9 Curing / 34.9
34.10 Liquid Photoimageable Solder Resist (LPISR) / 34.9
34.10.1 LPISR Makers and Products / 34.10
34.10.2 Coating Methods / 34.11
34.10.3 Panel Preparation / 34.12
34.10.4 Screen Coating / 34.12
34.10.5 Curtain Coating / 34.14
34.10.6 Spray Coating / 34.15
34.11 Tenting Holes / 34.16
34.12 Electroless Nickel/Gold Plating Issues for Solder Resists / 34.16
Chapter 35. Machining and Routing 35.1
35.1 Introduction / 35.1
35.2 Punching Holes (Piercing) / 35.1
35.2.1 Design of the Die / 35.1
35.2.2 Shrinkage of Paper-Base Laminates / 35.2
35.2.3 Tolerance of Punched Holes / 35.2
35.2.4 Hole Location and Size / 35.3
35.2.5 Warming Paper-Base Material / 35.3
35.2.6 Press Size / 35.3
35.3 Blanking, Shearing, and Cutting of Copper-Clad Laminates / 35.4
35.3.1 Blanking Paper-Base Laminates / 35.4
35.3.2 Blanking Glass-Base Laminates / 35.4
35.3.3 Shearing / 35.4
35.3.4 Sawing Paper-Base Laminates / 35.5
35.3.5 Sawing Glass-Base Laminates / 35.6
35.4 Routing / 35.6
35.4.1 Pin Routing / 35.6
35.4.2 CNC Routing Applications / 35.6
35.4.3 Computer Numerical Controlled (CNC) Operation / 35.7
35.4.4 Cutter Offset / 35.9
35.4.5 Direction of Cut / 35.10
35.4.6 Cutter Speed and Feed Rate / 35.10
35.4.7 Cutter Bits / 35.10
35.4.8 Tooling / 35.11
35.4.9 Cutting and Holding Techniques / 35.12
35.5 Scoring / 35.13
35.5.1 Scoring Application / 35.13
35.5.2 Operation / 35.14
CONTENTS xxi
Chapter 36. Process Capability and Control 36.1
36.1 Introduction / 36.1
36.1.1 Circuit Density / 36.1
36.1.2 Supplier Capability and Quality / 36.2
36.1.3 Design for Manufacturability / 36.2
36.2 Measuring Capability and Quality / 36.3
36.2.1 Process Capability Test Panels / 36.3
36.2.2 Testing Methods / 36.4
36.3 Data Analysis Techniques / 36.5
36.3.1 Defect Density / 36.5
36.3.2 Predicted Yields / 36.5
36.3.3 Capability Potential Index / 36.5
36.3.4 Capability Performance Index / 36.5
36.3.5 Coefficient of Variation / 36.6
36.3.6 Probability of Breakout / 36.6
36.4 Conductor and Space Capability and Quality / 36.6
36.5 Via Capability and Quality / 36.9
36.6 Solder Mask Registration Capability / 36.12
36.7 Controlled-Impedance Capability / 36.13
36.8 Standardization / 36.15
Chapter 37. Bare Board Test Objectives and Definitions 37.1
37.1 Introduction / 37.1
37.2 The Impact of HDI / 37.1
37.3 Why Test? / 37.2
37.3.1 The Rule of 10s / 37.2
37.3.2 Satisfying Customer Requirements / 37.2
37.3.3 Electrical Testing as a Process Monitor / 37.4
37.3.4 Quality System Improvement / 37.4
37.4 Circuit Board Faults / 37.4
37.4.1 Fault Types / 37.5
Chapter 38. Bare Board Test Methods 38.1
38.1 Introduction / 38.1
38.2 Nonelectrical Testing Methods / 38.1
38.2.1 Visual Inspection / 38.1
38.2.2 Automatic Optical Inspection / 38.1
38.3 Basic Electrical Testing Methods / 38.2
38.3.1 DC Continuity Test Methods / 38.2
38.3.2 DC Isolation Test Methods / 38.5
38.4 Specialized Electrical Test Methods / 38.9
38.4.1 Hi-Pot Testing / 38.9
38.4.2 Embedded Component Test Methods / 38.10
38.4.3 Time Domain Reflectometry (TDR) / 38.10
38.4.4 Test Methods Unique To Flying Probe Systems / 38.11
38.5 Data and Fixture Preparation / 38.13
38.5.1 Self-Learning / 38.13
38.5.2 Data-Driven Testing / 38.14
38.5.3 Data Formats / 38.16
38.5.4 Outputs from Data Extraction / 38.17
38.5.5 Setting Up a Fixture / 38.18
38.6 Combined Test Methods / 38.19
38.6.1 Split Net Testing / 38.19
38.6.2 Manual Combination of Methods / 38.19
38.6.3 Integrated Sequential Testing / 38.20
xxii CONTENTS
Chapter 39. Bare Board Test Equipment 39.1
39.1 Introduction / 39.1
39.2 System Alternatives / 39.1
39.2.1 Fixtured Systems / 39.1
39.2.2 Dedicated (Hard-Wired) Fixture Systems / 39.1
39.2.3 Flying Probe-Type Test Systems / 39.3
39.3 Universal Grid Systems / 39.3
39.3.1 Universal Grid Test System Design / 39.4
39.3.2 Exclusion Mask Fixtures for Universal Grid Systems / 39.4
39.3.3 Pin Translator Fixtures for Universal Grid Systems / 39.4
39.3.4 Dual-Side Testing Considerations / 39.15
39.3.5 Press Units / 39.17
39.4 Flying Probe/Moving Probe Systems / 39.17
39.4.1 Advantages of Flying Probe Systems / 39.18
39.4.2 Economics of Flying Probe Systems / 39.19
39.5 Verification and Repair / 39.19
39.6 Test Department Planning and Management / 39.20
39.6.1 Equipment Selection / 39.21
39.6.2 Fixtures: Build or Buy, and What Type? / 39.21
39.6.3 Selecting Fixture Software / 39.21
Chapter 40. HDI Bare Board Special Testing Methods 40.1
40.1 Introduction / 40.1
40.2 Fine-Pitch Tilt Pin Fixtures / 40.1
40.3 Bending Beam Fixtures / 40.2
40.4 Flying Probe / 40.3
40.5 Scanning Contact / 40.3
40.6 Coupled Plate / 40.4
40.7 Shorting Plate / 40.5
40.8 Conductive Rubber Fixtures / 40.5
40.9 Optical Inspection / 40.5
40.10 Noncontact Test Methods / 40.6
40.10.1 Electron Beam Methods / 40.6
40.10.2 Photoelectric Methods / 40.6
40.10.3 Gas Plasma Methods / 40.7
40.11 Combinational Test Methods / 40.7
Part 6 Assembly
Chapter 41. Assembly Processes 41.3
41.1 Introduction / 41.3
41.1.1 The Density Revolution / 41.3
41.1.2 Printed Circuit Assembly / 41.3
41.2 Insertion Mount Technology / 41.4
41.2.1 Introduction / 41.4
41.2.2 Design Considerations / 41.4
41.2.3 Assembly Process / 41.5
41.2.4 Cells vs. Process Lines / 41.9
41.2.5 Insertion Machine Architectures / 41.10
41.3 Surface-Mount Technology / 41.11
41.3.1 Assembly Process / 41.11
41.3.2 Component Placement Machines / 41.11
41.3.3 Machine Vision Technology / 41.15
41.3.4 Machine Vision Operating Overview / 41.16
CONTENTS xxiii
41.3.5 The Function of Machine Vision in the Surface-Mount Process / 41.16
41.3.6 Line Architecture / 41.18
41.3.7 Dispensing / 41.19
41.4 Odd-Form Assembly / 41.24
41.4.1 Overview / 41.24
41.4.2 Manual Assembly / 41.25
41.4.3 Automation / 41.26
41.4.4 Components / 41.27
41.4.5 Component Packaging / 41.28
41.4.6 Equipment / 41.31
41.5 Direct Chip Attach / 41.32
41.5.1 Overview / 41.32
41.5.2 Types / 41.32
41.6 Accuracy and Repeatability / 41.33
41.6.1 Considerations / 41.33
41.6.2 Definitions / 41.33
41.7 Network Communication / 41.34
41.7.1 Overview / 41.34
41.7.2 Protocol Functions / 41.34
41.8 Key Machine Selection Criteria / 41.38
41.8.1 Cost of Ownership / 41.38
41.8.2 Utilization / 41.38
Part 7 Soldering
Chapter 42. Design for Soldering and Solderability 42.3
42.1 Introduction / 42.3
42.2 Design Considerations / 42.3
42.2.1 Wire-to-Hole Ratio / 42.3
42.2.2 Size and Shape of the Land Area / 42.3
42.2.3 Number and Direction of Extended Parallel Lines / 42.4
42.2.4 Population Distribution / 42.4
42.3 Material Systems / 42.4
42.3.1 Common Metallic Surfaces / 42.4
42.4 Wetting and Solderability / 42.5
42.5 Solderability Testing / 42.6
42.5.1 Testing Procedures / 42.7
42.5.2 Standard Solderability Tests / 42.8
42.6 Plated Coatings for Preserving Solderability / 42.9
42.6.1 Fusible Coatings / 42.9
42.6.2 Soluble Coatings / 42.10
42.6.3 Nonfusible and Nonsoluble Coatings / 42.11
42.6.4 Organic Coatings / 42.11
42.7 Tin-Lead Fusing / 42.11
42.7.1 Thick Fused Coatings / 42.12
42.7.2 Thin Fused Coatings / 42.12
42.7.3 Problems in Reflowing Plated Coatings / 42.12
42.8 Solderability and the Plating Operation / 42.13
42.8.1 Effect of Organic Plating Additives / 42.13
42.8.2 Effect of the Plating Anode / 42.14
42.9 Use of Precleaners to Restore Solderability / 42.14
42.9.1 Causes of Poor Solderability / 42.14
42.9.2 Cleaning Tin-Lead Surfaces / 42.15
xxiv CONTENTS
Chapter 43. Solder Materials and Processes 43.1
43.1 Introduction / 43.1
43.1.1 Designing for Process and Product / 43.4
43.1.2 Common Metal-Joining Methods / 43.5
43.2 Soldering / 43.6
43.2.1 Application of Heat to Solder / 43.6
43.2.2 Oxidation Formation / 43.7
43.2.3 Chemical Preparation of Solder Surfaces / 43.7
43.2.4 Solder Wetting/Intermetallic Formation / 43.7
43.2.5 Solder Quenching / 43.7
43.3 Solder Fillets / 43.8
43.4 Intermetallic Compounds and Metallurgy / 43.9
43.5 Soldering Techniques / 43.9
43.5.1 Mass Soldering Methods / 43.10
43.6 Oven Reflow Soldering / 43.12
43.6.1 Reflow Oven Subsystems / 43.12
43.6.2 Forced-Air Convection Reflow Oven / 43.17
43.6.3 Cooling / 43.18
43.6.4 Venting / 43.19
43.6.5 Reflow Oven Characteristics / 43.20
43.6.6 Reflow Profile / 43.21
43.6.7 Success in Reflow / 43.24
43.6.8 Product Profile Board / 43.26
43.6.9 Oven Diagnostic Board / 43.26
43.6.10 Printed Circuit Board Thermometry / 43.26
43.6.11 Reflow Profiler or Tracker / 43.29
43.6.12 Atmospheres for Reflow / 43.30
43.7 Wave Soldering / 43.31
43.7.1 Types of Wave-Soldering Systems / 43.32
43.7.2 Flux Application for Wave Soldering / 43.33
43.7.3 Flux Application Techniques / 43.33
43.7.4 Preheating / 43.34
43.7.5 The Wave as a Process / 43.35
43.7.6 Dross / 43.36
43.7.7 Metal Contaminants / 43.37
43.7.8 Design for Wave Soldering / 43.37
43.8 Vapor-Phase Reflow Soldering / 43.40
43.8.1 Basic Process / 43.40
43.8.2 Machine Subsystems / 43.41
43.8.3 Advantages/Disadvantages / 43.41
43.9 Laser Reflow Soldering / 43.42
43.9.1 Laser Soldering Applications / 43.42
43.9.2 Lasers / 43.43
43.9.3 Criteria for Lasers for Soldering / 43.45
43.9.4 Laser Alternatives / 43.45
43.9.5 Carbon Dioxide (CO2) Lasers / 43.46
43.9.6 YAG Lasers / 43.47
43.9.7 Laser-Soldering Fundamentals / 43.47
43.9.8 Through-Lead vs.Through-Pad Bonding / 43.48
43.9.9 Laser Solder Joint Characteristics / 43.52
43.9.10 Solder Sources and Defects Associated with Laser Reflow / 43.53
43.9.11 Laser Safety Issues / 43.53
43.10 Hot-Bar Soldering / 43.54
43.10.1 Solder Application / 43.54
43.10.2 Fluxes and Fluxing / 43.54
43.10.3 The Soldering Operation / 43.55
43.10.4 Construction / 43.55
43.10.5 Hot-Bar Design and Materials / 43.56
43.10.6 Maintenance and Diagnostic Methods / 43.58
CONTENTS xxv
43.11 Hot-Gas Soldering / 43.59
43.12 Ultrasonic Soldering / 43.61
43.13 Repair and Rework / 43.62
43.13.1 Hot Gas / 43.62
43.13.2 Solder Fountain / 43.64
43.13.3 Laser / 43.64
43.13.4 Considerations for Repair / 43.64
References / 43.65
Chapter 44. No-Clean Assembly Process 44.1
44.1 Introduction / 44.1
44.2 Definition of No-Clean / 44.1
44.2.1 Definition of Low-Residue No-Clean Process / 44.2
44.2.2 Definition of a Leave-On No-Clean Process / 44.2
44.3 Cleaning or No-Clean? / 44.2
44.4 Implementing No-Clean / 44.4
44.4.1 Incoming Quality Assurance (IQA) / 44.5
44.4.2 Stencil Aperture Design and Stencil Finish / 44.5
44.4.3 Stencil Washing / 44.5
44.4.4 Cleaning Misprinted PCBs / 44.6
44.4.5 Stencil Printing / 44.6
44.4.6 Pick and Place / 44.6
44.4.7 Nitrogen / 44.7
44.4.8 Reflow / 44.7
44.4.9 Wave Solder / 44.8
44.4.10 Hand Soldering / 44.10
44.4.11 In-Circuit Testing / 44.10
44.5 Reliability of No-Clean Products / 44.10
44.5.1 Surface Insulation Resistance Testing for No-Clean / 44.11
44.5.2 Ionic Contamination Testing for No-Clean / 44.11
44.5.3 Highly Accelerated Stress Testing (HAST) for No-Clean / 44.12
44.6 The Impact of No-Clean on Printed Circuit Board Fabrication / 44.12
44.7 Troubleshooting the No-Clean Process / 44.13
References / 44.15
Chapter 45. Lead-Free Soldering 45.1
45.1 Introduction / 45.1
45.1.1 Tin/Lead Solder Alloys / 45.1
45.1.2 Candidate Metals for Solder Alloys / 45.1
45.2 The Impetus to Eliminate or Reduce Lead / 45.2
45.3 The Role of Lead in the Solder Joint / 45.2
45.4 The Impact of Going Lead Free / 45.3
45.4.1 Impact on Wave Soldering / 45.3
45.4.2 Impact on Components / 45.3
45.4.3 Supply Constraint Impact / 45.4
45.4.4 Impact of Oxidation / 45.4
45.4.5 Impact on Solder Flux / 45.4
45.4.6 Impact on Electrical Testing / 45.4
45.4.7 Impact on PWB Laminate / 45.4
45.4.8 Impact on Other Materials and Processes / 45.5
45.5 Surface Finishes / 45.5
45.5.1 Hot-Air Solder-Leveled Surfaces / 45.5
45.5.2 OSP-Copper / 45.5
45.6 Alloy Systems / 45.5
45.7 Candidate Lead-Free Solders / 45.6
45.8 Financial Impact of Lead-Free and Legal Constraints / 45.7
45.9 Characteristics of Lead-Free Solders / 45.8
45.10 Recommendations / 45.9
References / 45.9
xxvi CONTENTS
Chapter 46. Fluxes and Cleaning 46.1
46.1 Introduction / 46.1
46.2 Assembly Process / 46.1
46.3 Soldering Flux / 46.3
46.3.1 Vehicle / 46.3
46.3.2 Solvent / 46.3
46.3.3 Activators / 46.4
46.3.4 Other Additives / 46.4
46.4 Flux Form vs. Soldering Process / 46.4
46.5 Rosin Flux / 46.4
46.6 Water-Soluble Flux / 46.6
46.7 Low-Solids Flux / 46.7
46.8 Cleaning Issues / 46.7
46.8.1 The Montreal Protocol / 46.7
46.8.2 Solvent Replacements / 46.8
46.9 Flux Characterization Text Methods / 46.9
46.9.1 Copper Mirror Test (TM 2.3.32) / 46.10
46.9.2 Halide Content (TM 2.3.33) / 46.11
46.9.3 Fluoride Test (TM 2.3.35) / 46.11
46.9.4 Qualitative Corrosion Test (TM 2.6.15) / 46.11
46.9.5 Surface Insulation Resistance Test (TM 2.6.3.3) / 46.11
46.10 Electrochemical Migration / 46.12
46.11 Summary / 46.14
References / 46.15
Chapter 47. Press-Fit Connections 47.1
47.1 Introduction / 47.1
47.1.1 Advantages of Press-fit Systems / 47.1
47.1.2 Press-Fit System Categories / 47.2
47.1.3 Press-Fit Design Issues / 47.2
47.2 Board Requirements / 47.4
47.2.1 Surface Finish / 47.4
47.2.2 Bare Copper / 47.6
47.3 Equipment Basics / 47.6
47.4 Pressing Cycle / 47.6
47.5 Pressing Routines / 47.8
47.5.1 Uncontrolled Pressing / 47.8
47.5.2 Press to Height / 47.9
47.5.3 Press to Force / 47.9
47.5.4 Press to Gradient / 47.9
47.6 Rework for Press-Fit Connectors / 47.9
47.6.1 Replacement Cycles / 47.10
47.6.2 Rework Tools / 47.10
47.7 PWB Design/Board Procurement Tips / 47.10
47.7.1 Design Tips / 47.10
47.7.2 Press-Fit Process Tips / 47.11
Part 8 Quality Control and Reliability
Chapter 48. Acceptability of Fabricated Boards 48.3
48.1 Introduction / 48.3
48.2 Developing Acceptability Criteria / 48.3
48.2.1 Basic Rules / 48.3
48.2.2 Inspection桰s It Necessary? / 48.4
CONTENTS xxvii
48.3 Developing the Acceptance Criteria Agreement / 48.4
48.3.1 Common Acceptance Standards / 48.4
48.3.2 Establishing a Team Environment / 48.4
48.3.3 Meeting Quality Assurance Requirements / 48.5
48.4 Use of Test Patterns / 48.5
48.5 Determination of Acceptability / 48.6
48.6 The Materials Review Board / 48.6
48.7 Visual Inspection / 48.7
48.7.1 Surface Defects / 48.7
48.7.2 Base Material Effects/Defects / 48.10
48.7.3 Resin Smear / 48.12
48.7.4 Registration, Layer to Layer: X-ray Method / 48.12
48.7.5 Plated Through-Holes: Roughness and Nodulation / 48.13
48.7.6 Eyelets / 48.13
48.7.7 Base Material Edge Roughness / 48.14
48.7.8 Solder Mask / 48.15
48.7.9 Visual Inspection / 48.15
48.8 Dimensional Inspection / 48.16
48.8.1 Annular Ring / 48.16
48.8.2 Conductor Width / 48.18
48.8.3 Conductor Spacing / 48.19
48.8.4 Edge Definition / 48.19
48.8.5 Hole Specifications / 48.19
48.8.6 Bow and Twist / 48.21
48.8.7 Conductor Pattern Integrity / 48.24
48.8.8 Contour Dimensions / 48.24
48.8.9 Plating Thickness / 48.25
48.8.10 Undercutting (After Fabrication) / 48.28
48.8.11 Outgrowth / 48.29
48.8.12 Etchback / 48.30
48.8.13 Registration Layer to Layer / 48.31
48.8.14 Flush Conductor, Printed Boards / 48.31
48.8.15 Summary / 48.31
48.9 Mechanical Inspection / 48.32
48.9.1 Plating Adhesion / 48.32
48.9.2 Solderability / 48.34
48.9.3 Alloy Composition / 48.34
48.9.4 Thermal Stress Solder Float Test / 48.34
48.9.5 Peel Strength / 48.35
48.9.6 Bond Strength (Terminal Pull) / 48.36
48.9.7 Cleanliness (Resistivity of Solvent Extract) / 48.36
48.9.8 Mechanical Inspection Attributes / 48.36
48.10 Electrical Inspection / 48.36
48.10.1 Continuity / 48.37
48.10.2 Insulation Resistance (Circuit Shorts) / 48.37
48.10.3 Current Breakdown, Plated Through-Holes / 48.37
48.10.4 Dielectric Withstanding Voltage / 48.38
48.10.5 Electrical Inspection Attributes / 48.38
48.11 Environmental Inspection / 48.38
48.11.1 Thermal Shock / 48.39
48.11.2 Moisture and Insulation Resistance / 48.39
48.12 Summary / 48.39
48.13 Test Specifications and Methods Related to Printed Boards / 48.40
48.14 General Specifications Related to Printed Boards / 48.41
References / 48.42
Chapter 49. Acceptability of Printed Circuit Board Assemblies 49.1
49.1 Understanding Customer Requirements / 49.1
49.1.1 Military,Telecommunications, and Consumer Specifications / 49.1
xxviii CONTENTS
CONTENTS xxix
49.1.2 ANSI/J-STD and IPC-A-610 Industry Standards / 49.3
49.1.3 Workmanship Manuals / 49.5
49.2 Handling to Protect the PCBA / 49.5
49.2.1 ESD Protection / 49.5
49.2.2 Contamination Prevention / 49.6
49.2.3 Physical Damage Prevention / 49.7
49.3 PCBA Hardware Acceptability Considerations / 49.7
49.3.1 Component Types / 49.7
49.3.2 Electrical Clearance / 49.14
49.3.3 Physical Damage / 49.15
49.4 Component Installation or Placement Requirements / 49.15
49.4.1 Plated-Through-Hole (PTH) Lead Installation / 49.15
49.4.2 Surface-Mount Technology (SMT) Placement / 49.17
49.4.3 Use of Adhesives / 49.21
49.5 Component and PCB Solderability Requirements / 49.22
49.6 Solder-Related Defects / 49.24
49.6.1 Plated-Through-Hole Solder Joint Minimum Acceptable Conditions / 49.24
49.6.2 Solder Balls or Solder Splash / 49.24
49.6.3 Dewetting and Nonwetting / 49.25
49.6.4 Missing and Insufficient Solder / 49.26
49.6.5 Solder Webbing and Bridging / 49.26
49.6.6 Lead Protrusion Problems / 49.27
49.6.7 Voids, Pits, Blowholes, and Pinholes / 49.27
49.6.8 Disturbed or Fractured Solder Joints / 49.28
49.6.9 Excess Solder / 49.28
49.6.10 Solder Requirements for Vias / 49.29
49.6.11 Soldering to Terminals / 49.29
49.7 PCBA Laminate Condition, Cleanliness, and Marking Requirements / 49.29
49.7.1 Laminate Conditions / 49.29
49.7.2 PCBA Cleanliness / 49.31
49.7.3 PCBA Marking Acceptability / 49.32
49.8 PCBA Coatings / 49.32
49.8.1 Conformal Coating / 49.32
49.8.2 Solder Mask / 49.33
49.9 Solderless Wrapping of Wire to Posts (Wire Wrap) / 49.33
49.9.1 Wrap Post / 49.33
49.9.2 Wire Wrap Connection / 49.33
49.9.3 Single Wire Wrap Spacing / 49.34
49.9.4 Multiple Wire Wrap Spacing / 49.34
49.10 PCBA Modifications / 49.34
49.10.1 Cut Traces / 49.35
49.10.2 Lifted Pins / 49.35
49.10.3 Jumper Wires / 49.35
References / 49.38
Chapter 50. Assembly Inspection 50.1
50.1 Introduction / 50.1
50.1.1 Visual Inspection / 50.1
50.1.2 Automated Inspection / 50.2
50.2 Reasons for Inspection / 50.3
50.2.1 Process Fault Coverage / 50.3
50.2.2 Customer Specifications / 50.3
50.2.3 Quick Defect Detection and Correction / 50.4
50.2.4 Statistical Process Control / 50.4
50.3 Visual Inspection / 50.4
50.3.1 General Inspection Issues / 50.5
50.3.2 Solder Joint Inspection Issues / 50.5
50.3.3 Standards for Visual Inspection / 50.7
50.3.4 Capabilities of Visual Inspection / 50.7
xxx CONTENTS
50.4 Automated Inspection / 50.9
50.4.1 Measurements by Automated Systems / 50.9
50.4.2 Types of Automated Process Test Systems / 50.11
50.5 Three-Dimensional Solder Paste Automated Process Test Systems / 50.11
50.5.1 Operating Principles / 50.11
50.5.2 Applications / 50.12
50.5.3 Advantages and Disadvantages / 50.12
50.6 Two-Dimensional Placement Automated Process Test Systems / 50.13
50.6.1 Operating Principles / 50.13
50.6.2 Applications / 50.13
50.6.3 Advantages and Disadvantages / 50.14
50.7 Solder Joint Automated Process Test Systems / 50.14
50.7.1 Optical Imaging Systems / 50.15
50.7.2 Transmission X-ray Systems / 50.16
50.7.3 Cross-Sectional X-ray Systems / 50.16
50.7.4 Advantages and Disadvantages for X-ray Inspection / 50.18
50.8 Implementation of Automated Process Test Systems / 50.20
50.9 Design Implications of Automated Process Test Systems / 50.21
50.9.1 Automated Board Handling Requirements / 50.21
50.9.2 Test Development Ease of Use Requirements / 50.21
References / 50.21
Chapter 51. Design for Testing 51.1
51.1 Introduction / 51.1
51.2 Definitions / 51.2
51.3 Ad Hoc Design for Testability / 51.2
51.3.1 Physical Access / 51.3
51.3.2 Logical Access / 51.3
51.4 Structured Design for Testability / 51.4
51.5 Standards-Based Testing / 51.5
51.5.1 IEEE 1149.1, Boundary-Scan for Digital Circuits / 51.6
51.5.2 IEEE 1149.4, Boundary-Scan for Mixed-Signal Circuits / 51.9
References / 51.12
Chapter 52. Loaded Board Testing 52.1
52.1 Introduction / 52.1
52.2 The Process of Test / 52.2
52.2.1 Test as a Sorting Process / 52.3
52.2.2 Test as a Repair Driver / 52.3
52.2.3 Test as a Process Monitor / 52.3
52.3 Definitions / 52.4
52.3.1 Defects, Faults, and Tests / 52.4
52.3.2 Performance Faults / 52.6
52.3.3 Manufacturing Defects / 52.6
52.3.4 Specification Failures / 52.7
52.4 Testing Approaches / 52.7
52.4.1 Testing Boards for Performance Faults / 52.7
52.4.2 Testing Boards for Manufacturing Defects / 52.9
52.4.3 Testing Boards for Specification Faults / 52.11
52.5 In-Circuit Test Techniques / 52.11
52.5.1 Analog In-Circuit Test / 52.11
52.5.2 Digital In-Circuit Test / 52.13
52.5.3 Manufacturing Defect Analyzer (MDA) / 52.15
52.5.4 General-Purpose In-Circuit Tester / 52.15
52.5.5 Combinational Tester / 52.16
52.6 Alternatives to Conventional Electrical Tests / 52.17
52.7 Tester Comparison / 52.19
References / 52.20
Chapter 53. Reliability of Printed Circuit Assemblies 53.1
53.1 Fundamentals of Reliability / 53.2
53.1.1 Definitions / 53.2
53.1.2 Reliability Testing / 53.4
53.2 Failure Mechanisms of PCBs and Their Interconnects / 53.4
53.2.1 PCB Failure Mechanisms / 53.4
53.2.2 Interconnect Failure Mechanisms / 53.13
53.2.3 Components / 53.18
53.3 Influence of Design on Reliability / 53.19
53.4 Impact of PCB Fabrication and Assembly on Reliability / 53.20
53.4.1 Effect of PCB Fabrication Processes / 53.20
53.4.2 Effects of Printed Circuit Assembly Processes / 53.23
53.5 Influence of Materials Selection on Reliability / 53.27
53.5.1 PCB / 53.27
53.5.2 Interconnect Material / 53.32
53.5.3 Components / 53.33
53.5.4 Conformal Coatings / 53.36
53.6 Burn-In, Acceptance Testing, and Accelerated Reliability Testing / 53.36
53.6.1 Design of Accelerated Reliability Tests / 53.37
53.6.2 Printed Circuit Board Reliability Tests / 53.39
53.6.3 Printed Circuit Assembly Reliability Tests / 53.42
53.7 Summary / 53.45
References / 53.45
Further Reading / 53.47
Chapter 54. Component-to-PWB Reliability 54.1
54.1 Introduction to Package Reliability / 54.1
54.1.1 Packaging Challenges / 54.1
54.1.2 Overview / 54.3
54.2 Variables that Impact Reliability / 54.5
54.2.1 Actual Product Environment / 54.5
54.2.2 Design Choices / 54.6
54.2.3 Package Design Parameters / 54.9
54.2.4 Substrate Material / 54.12
54.3 Experimental Tools for Estimating Solder Joint Life / 54.14
54.3.1 Thermal Cycle / 54.14
54.3.2 Thermal Shock / 54.15
54.3.3 Mechanical Shock and Vibration / 54.16
54.3.4 Ball Shear/Pull / 54.16
54.4 Rapid Assessment Tools / 54.16
54.4.1 Norris-Landsberg Acceleration Transformation / 54.16
54.4.2 Finite Element Analysis / 54.20
54.5 Power and Minicycles / 54.22
54.5.1 Overview / 54.22
54.5.2 Miner抯 Rule / 54.22
54.6 Accelerated Stress Testing / 54.23
54.7 Practical Examples / 54.23
54.7.1 Comparing the Reliability of Two Packages Qualified Under Different Thermal Conditions / 54.23
54.7.2 Assessing Expected Field Life of a New Package Based on Thermal Cycle Data / 54.24
References / 54.26
CONTENTS xxxi
Part 9 Environmental Issues and Waste Treatment
Chapter 55. Process Waste Minimization and Treatment 55.3
55.1 Introduction / 55.3
55.2 Regulatory Compliance / 55.3
55.2.1 Clean Water Act / 55.4
55.2.2 Clean Air Act / 55.4
55.2.3 Resource Conservation and Recovery Act / 55.5
55.3 Major Sources and Amounts of Wastewater in a Printed Circuit Board Fabrication Facility / 55.5
55.3.1 Major Sources of Waste / 55.5
55.3.2 Typical Amounts of Waste Materials / 55.6
55.4 Waste Minimization / 55.6
55.4.1 Definitions / 55.6
55.5 Pollution Prevention Techniques / 55.8
55.5.1 Rinse Water Reduction / 55.9
55.5.2 Extended Bath Life / 55.11
55.5.3 Dragout Reduction / 55.13
55.5.4 Material Substitution / 55.14
55.6 Recycling and Recovery Techniques / 55.15
55.6.1 Copper Sulfate Crystallization / 55.15
55.6.2 Rinse Water Recycling / 55.15
55.6.3 Copper Recovery via Electrowinning / 55.16
55.7 Alternative Treatments / 55.18
55.7.1 Selective Ion Exchange / 55.18
55.7.2 Removal of Copper from the Electroless Copper Bath / 55.19
55.7.3 Sodium Borohydride Reduction / 55.19
55.7.4 Aqueous and Semiaqueous Photoresist Stripping Bath Treatment / 55.20
55.8 Chemical Treatment Systems / 55.21
55.8.1 Definition / 55.21
55.8.2 Treatment Process / 55.21
55.8.3 Collection System / 55.21
55.8.4 pH Adjust / 55.21
55.8.5 Settling Process / 55.26
55.8.6 Cross-Flow Microfiltration / 55.26
55.8.7 Sludge Thickening and Dewatering / 55.26
55.9 Advantages and Disadvantages of Various Treatment Alternatives / 55.26
Part 10 Flexible Circuits
Chapter 56. Flexible Circuits: Applications and Materials 56.3
56.1 Introduction to Flexible Circuits / 56.3
56.1.1 Advantages and Disadvantages of Flexible Circuits / 56.3
56.1.2 Economies of Flexible Circuits / 56.3
56.2 Applications of Flexible Circuits / 56.6
56.3 High-Density Flexible Circuits / 56.6
56.3.1 Specifications / 56.6
56.3.2 Applications / 56.7
56.4 Materials for Flexible Circuits / 56.8
56.4.1 Traditional Flexible Circuit Materials / 56.8
56.4.2 HDI-Oriented Flexible Circuit Materials / 56.8
56.5 Substrate Material Properties / 56.9
56.5.1 Comparison of Substrate Materials / 56.9
56.5.2 Polyimide Film / 56.9
56.5.3 Polyester Film / 56.11
56.5.4 Other Materials Used for Flexible Circuits / 56.11
xxxii CONTENTS
56.6 Conductor Materials / 56.13
56.7 Copper-Clad Laminates / 56.13
56.7.1 Adhesive-Based Laminates / 56.14
56.7.2 Adhesiveless-Based Laminates / 56.15
56.8 Coverlay Materials / 56.18
56.8.1 Film Coverlay / 56.18
56.8.2 Screen-Printable Coverlay Ink (Flexible Solder Mask) / 56.18
56.8.3 Dry Film-Type Photoimageable Coverlay / 56.18
56.8.4 Liquid-Base Photoimageable Coverlay / 56.21
56.9 Stiffener Materials / 56.21
56.10 Adhesive Materials / 56.22
Chapter 57. Design of Flexible Circuits 57.1
57.1 Introduction / 57.1
57.2 Design Procedure / 57.1
57.3 Types of Flexible Circuits / 57.2
57.3.1 High-Density Flexible Circuits / 57.2
57.3.2 Single-Sided Circuits / 57.4
57.3.3 Coverlay System of Flexible Circuits / 57.5
57.3.4 Surface Treatment Alternatives / 57.5
57.3.5 Double-Sided Circuits with Through-Holes / 57.6
57.3.6 Multilayer Rigid/Flex / 57.7
57.3.7 Flying-Lead Construction / 57.8
57.3.8 Microbump Arrays / 57.9
57.4 Circuit Designs for Flexibility / 57.9
57.5 Electrical Design of the Circuits / 57.11
57.6 Circuit Designs for Higher Reliability / 57.14
Chapter 58. Manufacturing of Flexible Circuits 58.1
58.1 Introduction / 58.1
58.2 Special Issues with High-Density Flexible Circuits / 58.1
58.3 Basic Process Elements / 58.2
58.3.1 Preparation of Materials / 58.3
58.3.2 Direct Cast Processes / 58.3
58.3.3 Mechanical Creation of Through-Holes / 58.4
58.3.4 Through-Hole Plating / 58.5
58.3.5 Microvia Hole Processes / 58.5
58.3.6 Surface Cleaning / 58.10
58.3.7 Resist Coating / 58.10
58.3.8 Pattern Generation / 58.10
58.3.9 Etching / 58.12
58.4 New Processes for Fine Traces / 58.12
58.4.1 Subtractive Process / 58.12
58.4.2 Semiadditive Processes / 58.13
58.4.3 Fully Additive Processes / 58.14
58.4.4 Process Comparison / 58.14
58.5 Coverlay Processes / 58.14
58.5.1 Film Coverlay / 58.14
58.5.2 Screen-Printing Coverlay / 58.16
58.5.3 Photoimageable Coverlay / 58.16
58.5.4 Laser-Drilling on Film Coverlay / 58.17
58.6 Surface Treatment / 58.20
58.7 Blanking / 58.22
58.8 Stiffener Processes / 58.23
58.9 Packaging / 58.23
58.10 Roll-to-Roll Manufacturing / 58.23
58.11 Dimension Control / 58.24
CONTENTS xxxiii
58.11.1 Materials / 58.24
58.11.2 Circuit Design / 58.25
58.11.3 Critical Processes for Dimension Control / 58.25
Chapter 59. Termination of Flexible Circuits 59.1
59.1 Introduction / 59.1
59.2 Selection of Termination Technologies / 59.1
59.2.1 Termination Objectives / 59.2
59.2.2 Nonpermanent or Permanent Termination / 59.3
59.2.3 Termination Density / 59.3
59.2.4 Wiring of Imaging Devices / 59.3
59.3 Permanent Termination / 59.4
59.3.1 Soldering / 59.4
59.3.2 Through-Hole Leaded Components / 59.4
59.3.3 SMT General Issues / 59.4
59.3.4 Solder Fusing / 59.6
59.3.5 Wire Bonding / 59.7
59.3.6 Direct Bonding / 59.7
59.3.7 Flip-Chip / 59.7
59.4 Semipermanent Connections / 59.8
59.4.1 Pressure Contact Termination / 59.9
59.4.2 Anisotropic Conductive Material / 59.10
59.5 Nonpermanent Connections / 59.11
59.5.1 General Connectors / 59.11
59.5.2 FFC Connectors for Flexible Circuits / 59.14
59.5.3 Bump Array Contacts and Dimple Array Contacts / 59.14
59.6 High-Density Flexible Circuit Termination / 59.15
Chapter 60. Special Constructions of Flexible Circuits 60.1
60.1 Introduction / 60.1
60.2 Multilayer Rigid/Flexible Circuits / 60.1
60.2.1 Basic Constructions / 60.1
60.2.2 Materials / 60.3
60.2.3 Manufacturing Processes Flow / 60.4
60.2.4 Through-Hole Process / 60.5
60.2.5 Build-up Process and Blind Via Holes / 60.6
60.2.6 Bookbinder Construction / 60.7
60.3 Flying-Lead Construction / 60.7
60.3.1 Basic Design / 60.7
60.3.2 Manufacturing Processes for Flying Leads / 60.8
60.3.3 Laser Processing / 60.9
60.3.4 Plasma Etching and Chemical Etching / 60.11
60.3.5 Economic Comparison / 60.12
60.4 Tape Automated Bonding / 60.13
60.4.1 Basic Concepts / 60.13
60.4.2 Manufacturing Processes / 60.14
60.5 Microbump Arrays / 60.14
60.5.1 Basic Design and Applications / 60.14
60.5.2 Manufacturing / 60.15
60.6 Thick-Film Conductor Flex Circuits / 60.15
60.6.1 Materials / 60.15
60.6.2 Applications / 60.15
60.6.3 Manufacturing Process / 60.15
xxxiv CONTENTS
Chapter 61. Quality Assurance of Flexible Circuits 61.1
61.1 Introduction / 61.1
61.2 Basic Concepts in Flexible Circuit Quality Assurance / 61.1
61.3 Automatic Optical Inspection Systems / 61.2
61.4 Dimensional Measurements / 61.2
61.5 Electrical Tests / 61.3
61.6 Inspection Sequence / 61.3
61.7 Raw Materials / 61.5
61.8 Flexible Circuit Feature Inspection / 61.6
61.8.1 Micro-Size Hole Generation / 61.6
61.8.2 Trace Quality / 61.6
61.8.3 Coverlay and Surface Treatments / 61.6
61.8.4 Microbump Arrays / 61.6
61.8.5 Flying Leads / 61.7
61.8.6 Electrical Testing (Opens/Shorts) / 61.7
61.8.7 Physical Properties (Final properties) / 61.7
61.8.8 Cosmetic Quality / 61.7
61.9 Standards and Specifications for Flexible Circuits / 61.8
61.9.1 IEC / 61.8
61.9.2 IPC / 61.9
61.9.3 JIS / 61.9
61.9.4 JPCA / 61.9
61.9.5 MIL / 61.9
61.9.6 UL / 61.9
Appendix A.1
Glossary G.1
Index I.1
About the Author I.16

LIST OF CONTRIBUTORS
Steven M. Allen AVEX Electronics, Fremont, CA (CHAP. 20)
A. D. Andrade Sandia National Laboratories, Livermore, CA (retired) (CHAP. 48)
Simon Ang University of Arkansas, Fayetteville,AR (CHAP. 3)
Joyce M. Avery Avery Environmental Services, Saratoga, CA (CHAP. 55)
Fred Barlow University of Arkansas, Fayetteville,AR (CHAP. 3)
Todd A. Barnett Excellon Automotive,Torrence, CA (CHAP. 25)
David W. Bergman IPC, Northbrook, IL (APPENDIX)
Bruce Bolliger Agilent Technologies, Singapore (CHAP. 50)
Richard Boulanger Universal Instruments, Binghamton, NY (CHAP. 41)
Mark Brillhart Cisco Systems, San Jose, CA (CHAP. 54)
William Brown University of Arkansas, Fayetteville,AR (CHAP. 3)
James Cadile NOVA Drilling Service, Santa Clara, CA (CHAP. 35)
Hugh Cole (CHAP. 42)
Brian F. Conaghan Parelec, Rocky Hill, NJ (CHAP. 26)
Edward F. Duffek Adion Engineering, Cupertino, CA (CHAP. 28)
C. D. DuPriest Lockheed Martin, Dallas,TX (CHAP. 27)
Sylvia Ehrler Multek Europe, Böblingen, Germany (CHAP. 12)
Timothy A. Estes Conductor Analysis Technologies, Albuquerque, NM (CHAP. 36)
Gary M. Freedman Compaq,Alpha High Performance Systems, Marlboro,MA (CHAPS. 43, 45, 47)
Judith Glazer Hewlett-Packard, Palo Alto, CA (CHAP. 53)
Ceferino G. Gonzalez Dupont, Research Triangle Park, NC (CHAP. 11)
Marshall I. Gurian Marshall Gurian Consulting,Tempe,AZ (CHAP. 33)
Paul W. Henderson Hewlett-Packard, Palo Alto, CA (CHAP. 44)
Charles G. Henningsen Insulectro, Mountain View, CA (CHAP. 35)
Ralph J. Hersey, Jr. Lawrence Livermore National Laboratory, Livermore, CA (CHAP. 15)
Happy T. Holden Westwood Associates, Loveland, CO (CHAPS. 1, 18, 21, 22)
Robert R. Holmes AT&T, Richmond,VA (CHAP. 17)
Edward J. Kelley Sanmina, Derry, NH (CHAPS. 5–10)
George Milad Shipley Ronal, Marlborough,MA (CHAPS. 29, 32)
Peter G. Moleux Peter Moleux and Associates, Newton Centre,MA (CHAP. 55)
Hayao Nakahara N.T. Information, Huntington, NY (CHAPS. 4, 23, 30, 31, 34)
Dominique K. Numakura DKN Research, Haverhill,MA (CHAPS. 56–61)
xxxvii
Stig Oresjo Agilent Technologies, Loveland, CO (CHAP. 50)
Kenneth P. Parker Agilent Technologies, Loveland, CO (CHAPS. 51, 52)
Clyde Parrish PC World,Toronto, Canada (CHAP. 19)
Tarak Railkar Conexant Systems, Newport Beach, CA (CHAP. 3)
Ronald J. Rhodes Conductor Analysis Technologies, Green Brook, NJ (CHAP. 36)
Lee W. Ritchey 3Com, Santa Clara, CA (CHAPS. 13, 14)
Michael Roesch Hewlett-Packard, Palo Alto, CA (CHAP. 12)
John W. Stafford JWS Consulting PLC, Phoenix,AZ (CHAP. 2)
Ken Taylor Polar Instruments, Garenne Park, Guernsey, UK (CHAP. 16)
Leland E. Tull Contouring Technology, Mountain View, CA (CHAP. 35)
Laura J. Turbini University of Toronto, Canada (CHAP. 46)
Hans Vandervelde Laminating Company of America, Garden Grove, CA (CHAP. 24)
David J. Wilkie Everett Charles Technologies, Pomona, CA (CHAPS. 37–40)
Warren Wong Excellon Automotive,Torrence, CA (CHAP. 25)
Bruce Wooldridge DSC Communications, Plano,TX (CHAP. 49)

PREFACE
There has been a “density revolution” in the technology of printed circuits.The need for ever
smaller board feature sizes has resulted in a situation in which we can no longer do the same
things in the same ways, only smaller. For geometries that meet or exceed the definition of
high-density interconnect (HDI), new approaches to design, fabrication, assembly, and testing
have been developed, and entirely new materials, tools, and processes have emerged. This
would seem to be the very definition of a technical revolution.
This edition of Printed Circuits Handbook addresses these new elements of the printed circuit
processes, while still maintaining its foundation on the basics of the technology. As a
result, almost one-quarter of the chapters in this book are new to this edition, while half have
been revised and expanded to include HDI-related information in the traditional process
areas.The result is a new book clearly founded on the basics, but looking to the future.
To achieve this, we have included new chapters on materials, design, microvia hole creation,
sequential build-up of multilayer boards, buried and blind via construction, small-geometry
imaging and plating, special assembly, and soldering, as well as testing of both fabricated and
assembled boards made with HDI feature size, and the reliability of these assemblies.
No matter how sophisticated the leading edge of the technology becomes, however, at the
core of all printed circuits is the plated through-hole in its various forms.This remains one of
the most important technical achievements of the twentieth century, and certainly one of the
least appreciated. It provides the means to interconnect, and therefore make useful, the complex
components that make up all the electronic products that are so much a part of daily life.
This represents the process elements that form the enduring foundation of printed circuit
technology. Printed circuits have evolved over the years to be more reliable, efficient, and
reproducible, but the process described in the first edition of this book is still recognizable in
the fifth.Therefore, those new to the technology will still find introductory information, while
experienced practitioners will find the industry standard methods and best practices that help
with the most recent developments. All will find a comprehensive discussion of HDI technologies,
materials, and methods to help them function in that complex field as well.
As the industry has grown, it has become more specialized. This has created the need to
standardize documentation and communication techniques as well as to understand the specific
capabilities of all suppliers in the overall value delivery chain. The result is that process
capabilities and limitations, at each step, must be known, the board must be designed with
these clearly in mind, and consistent acceptability criteria must be agreed to in advance,
before the responsibility for the board passes from designer to fabricator to assembler to end
user. This has created a community of people who have not been intimately involved in
printed circuit issues before, and who now find a working knowledge of printed circuits critical
for their performance.This book provides information for these people as well.They will
not only find the basic information useful in understanding the issues, but there are also specific
guidelines on the development and management of the value chain for the success of all.
While the industry’s preferred term for the subject of this book is printed wiring, the term
printed circuits has passed into the world’s languages as representing the process and products
described. As a result, we will use the terms interchangeably.
I wish to thank the staff of the IPC, especially Dieter Bergman, David Bergman, and Tony
Hilvers, for their efforts in support of this book.While not directly involved here, Ray Pritchard,
retired executive director of the IPC, remains a strong influence on all of us in the industry.
Clyde F. Coombs, Jr.

PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief

PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief

PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief

PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief

PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief

PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Editor-in-Chief

好多内容哦

看来需要花几个月才能看完了！

感谢分享

感谢楼主分享好书。
打印出来的电路，嘛意思

Very good, thanks a lots LZ

不错，先下了！！！！！！！！！！

支持一下。。。。。。。。

多谢。。。。。。。。

多谢楼主，实在是好啊！！！！！！！！！！！！！！！！

谢谢楼主分享，学习学习。:11bb :27bb :29bb

感谢楼主分享

感谢楼主分享好书。

好多内容哦

看来需要花几个月才能看完了！

Nice PCB Book.
5 th ed.

好多啊啊

谢谢分享