Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and fundamental Performance Limits
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Author:James A. Cherry, W. Martin Snelgrove
| Springer 1999
| ISBN: 0792386256
| 248 pages
| PDF, 8.03 Mb
Price:$235.00
Contents:
一. ∆∑M CONCEPTS
1. A Brief Introduction to ∆∑M
1.1 Operating Principles
1.2 Design Choices
2. Why Continuous-Time ∆∑M?
3. Performance Measures
3.1 Power Spectrum Estimation
3.2 Signal to Noise Ratio (SNR)
3.3 Other Performance Measures
4. Simulation Methods
4.1 Discrete-Time Modulator Simulation
4.2 Continuous-Time Modulator Simulation
5. Summary
二. DESIGNING CT MODULATORS
1. Ideal ∆∑M Design
1.1 The Impulse-Invariant Transform
1.2 Exploiting the Equivalence
1.3 Band Pass Modulators
2. Implicit Antialias Filters
3. Unequal DAC Pulse Rise/Fall Time
4. Practical Design and Characterization
4.1 SPICE-Based Feedback Setting
4.2 SPICE Design Dual: z-Domain Extraction
5. Summary
三. ∆∑M IMPLEMENTATION ISSUES
1. Nonidealities in ∆ΣMs
1.1 Op Amps
1.2 Mismatch and Tolerance
1.3 Quantizers
1.4 Circuit Noise
1.5 Other Nonidealities
2. A Survey of Important CT ∆ΣM Papers
3. High-Speed CT ∆ΣM Performance
4. Summary
四. EXCESS LOOP DELAY
1. Effect of Excess Loop Delay
2. Double Integration Modulator
2.1 Root Locus
2.2 In-Band Noise
2.3 Maximum Stable Amplitude
2.4 Dynamic Range
3. fs /4 Fourth-Order Band Pass Modulator
4. Higher-Order Modulators
5. Modulators with a Multibit Quantizer
6. Compensating for Excess Loop Delay
6.1 DAC Pulse Selection
6.2 Feedback Coefficient Tuning
6.3 Additional Feedback Parameters
7. Summary
五. JITTER AND METASTABILITY
1. Preliminaries
1.1 Jitter in CT Modulators
1.2 Modulator Architecture
1.3 Simulation Method
2. White Clock Jitter
2.1 LP Modulators with NRZ Feedback
2.2 Modulators with RZ and/or HRZ Feedback
3. Clocking with a VCO
3.1 Modeling VCO Phase Noise
3.2 Effect of Accumulated Jitter on Performance
4. Latches and Metastability
4.1 Digital Circuits vs. ∆ΣMs
4.2 Characterization Method for ∆ΣMs
4.3 Validation of Quantizer Model
5. Real Quantizer Performance Effects
6. Mitigating Metastability Performance Loss
6.1 Parameter Scaling
6.2 Regeneration Time
6.3 Preamplification
6.4 Additional Latching Stages
6.5 Other Modulator Architectures
7. Maximum Clocking Frequency
8. Summary
六. BP ∆ΣM DESIGN PROCEDURE
1. Design Problem Statement
2. Input Transconductor Gg1
3. Tank Components and Gq
4. Feedback DAC Currents and Gg 2
5. Linearity of Internal Transconductors
6. Summary
七. A 4GHZ 4TH-ORDER BP ∆ΣM
1. Parameters for This Design
2 . Circuit Blocks
2.1 Resonator
2.2 Latch
2.3 Output Buffer
2.4 DAC
2.5 Complete Circuit
3 . Measurement Results
3.1 Resonator
3.2 Latch
3.3 Output Buffer
3.4 DAC
3.5 Dynamic Range
4 . Result Commentary
5. Summary
八. CONCLUSIONS
1. Summary of Results
2. Usefulness of High-Speed CT ∆ΣM
3. Future Work
学习..............................
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